参数资料
型号: ADS8361IDBQG4
厂商: Texas Instruments
文件页数: 5/29页
文件大小: 0K
描述: IC ADC DUAL 16BIT 500KSPS 24QSOP
产品培训模块: Data Converter Basics
标准包装: 50
位数: 16
采样率(每秒): 500k
数据接口: 串行
转换器数目: 2
功率耗散(最大): 200mW
电压电源: 模拟和数字
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
输入数目和类型: 8 个单端,双极;4 个差分,双极
配用: 296-19922-ND - EVAL MOD FOR ADS8361
ADS8361
13
SBAS230E
www.ti.com
tion). Twenty clock cycles are required to perform a single
conversion. Immediately following CONVST switching to
HIGH, the ADS8361 will switch from the sample mode to the
hold mode asynchronous to the external clock. The BUSY
output pin will then go HIGH and remain HIGH for the
duration of the conversion cycle. On the falling edge of the
first cycle of the external clock, the ADS8361 will latch in the
address for the next conversion cycle depending on the
status of the A0 pin (HIGH = Channel 1, LOW = Channel 0).
The address must be selected 15ns prior to the falling edge of
cycle one of the external clock and must remain ‘held’ for 15ns
following the clock edge. For maximum throughput time, the
CONVST and RD pins should be tied together. CS must be
brought LOW to enable the CONVST and RD inputs. Data will
be valid on the falling edge of all 20 clock cycles per conver-
sion. The first bit of data will be a status flag for either Channel
0 or 1, the second bit will be a second status flag for either
Channel A or B. First and second bit will be 0 in Mode I. See
Table II below. The subsequent data will be MSB-first through
the LSB, followed by two zeros (see Table III and Figures 9
and 10).
CLOCK CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SERIAL DATA CH0 OR CH1 CHA OR CHB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2 DB1
DB0
0
TABLE III. Serial Data Output Format.
FIGURE 8. Ideal Conversion Characteristics (Condition: Single Ended, VCM = chXX– = 2.5V, VREF = 2.5V)
BIT 1
BIT 2
MODE
M0
M1
CH0/1
CHA/B
CHANNEL SELECTION
DATA OUTPUT
10000
Ch0/1 Selected by A0
On Data A and B
2010
0 = A/1 = B
Ch0/1 Selected by A0
Sequentially on Data A
3
1
0
0/1
0
Ch0/1 Alternating
On Data A and B
4
1
0/1
0 = A/1 = B
Ch0/1 Alternating
Sequentially on Data A
TABLE II. Mode Selection.
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
1111 1111 1111 1111
Binary Two’s Complement
BTC
Digital
Output
Code
VNFS = VCM – VREF = 0V
0.000038V
0.000076V
0.000152V
2.499962V
2.500038V
VBPZ = 2.5V
Unipolar Analog Input Voltage
1LSB = 76μV
VCM = 2.5V
VREF = 2.5V
4.999848V
VPFS – 1LSB = 4.999924V
VPFS = VCM + VREF = 5V
0
1
2
32767
32768
32769
65533
65534
65535
Step
16-BIT
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code
Bipolar Zero Code
Positive Full-Scale Code
= VNFS = 8000H, Vcode = VCM – VREF
= VBPZ = 0000H, Vcode = VCM
= VPFS = 7FFFH, Vcode = (VCM + VREF)– 1LSB
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