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| 型号： | ADSP-2115BPZ-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 63/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 68-PLCC |
| 标准包装： | 19 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 同步串行端口（SSP） |
| 时钟速率： | 25MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 3kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC（24.23x24.23） |
| 包装： | 管件 |
| 产品目录页面： | 738 (CN2011-ZH PDF) |
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ADSP-21xx
–8–
REV. B
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
Reset
The RESET
signal initiates a complete reset of the ADSP-21xx.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
Table IV. ADSP-21xx Pin Definitions
Pin
# of
Input /
Name(s)
Pins
Output
Function
Address
14
O
Address outputs for program, data and boot memory.
Data
1
24
I/O
Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.
RESET
1
I
Processor Reset Input
IRQ2
1
I
External Interrupt Request #2
BR
2
1
I
External Bus Request Input
BG
1
O
External Bus Grant Output
PMS
1
O
External Program Memory Select
DMS
1
O
External Data Memory Select
BMS
1
O
Boot Memory Select
RD
1
O
External Memory Read Enable
WR
1
O
External Memory Write Enable
MMAP
1
I
Memory Map Select Input
CLKIN, XTAL
2
I
External Clock or Quartz Crystal Input
CLKOUT
1
O
Processor Clock Output
VDD
Power Supply Pins
GND
Ground Pins
SPORT0
3
5
I/O
Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)
SPORT1
5
I/O
Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)
or Interrupts & Flags:
IRQ0
(RFS1)
1
I
External Interrupt Request #0
IRQ1
(TFS1)
1
I
External Interrupt Request #1
FI (DR1)
1
I
Flag Input Pin
FO (DT1)
1
O
Flag Output Pin
FL2–0 (ADSP-2111 Only)
3
O
General Purpose Flag Output Pins
Host Interface Port
(ADSP-2111 Only)
HSEL
1
I
HIP Select Input
HACK
1
O
HIP Acknowledge Output
HSIZE
1
I
8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)
BMODE
1
I
Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)
HMD0
1
I
Bus Strobe Select (0 = RD/WR, 1 = RW/DS)
HMD1
1
I
HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)
HRD
/HRW
1
I
HIP Read Strobe or Read/Write Select
HWR
/HDS
1
I
HIP Write Strobe or Host Data Strobe Select
HD15–0/HAD15-0
16
I/O
HIP Data or HIP Data and Address
HA2/ALE
1
I
Host Address 2 Input or Address Latch Enable Input
HA1–0/Unused
2
I
Host Address 1 and 0 Inputs
NOTES
1Unused data bus lines may be left floating.
2BR must be tied high (to V
DD) if not used.
3ADSP-2105 does not have SPORT0. (SPORT0 pins are No Connects on the ADSP-2105.)
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