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参数资料
| 型号： | ADSP-21160NCB-100 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400BGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 100MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.90V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
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–41–
REV. 0
ADSP-21160N
where:
P
EXT is from Table 30
P
INT is IDDINT × 1.9 V, using the calculation IDDINT listed in
Power Dissipation on Page 40
P
PLL is AIDD × 1.9 V, using the value for AIDD listed in
ABSOLUTE MAXIMUM RATINGS on Page 15
Note that the conditions causing a worst-case PEXT are different
from those causing a worst-case PINT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in ADSP-
21160N specifications on Page 14 include output disable time,
output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L and the
load current, IL. This decay time can be approximated by the
following equation:
tDECAY = (CL
V)/I
L
The output disable time tDIS is the difference between tMEASURED
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. tDECAY is calculated with test loads CL and IL,
and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time tENA is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 28). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
V
to be the difference between the ADSP-21160N’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L is the total bus capacitance (per data
line), and IL is the total leakage or three-state current (per data
line). The hold time will be tDECAY plus the minimum disable time
(i.e., tDATRWH for the write cycle).
Table 30. External Power Calculations (3.3 V Device)
Pin Type
No. of Pins
% Switching
× C
× f
× VDD
2
= PEXT
Address
15
50
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.088 W
MS0
1
0
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.000 W
WRx
2
× 44.7 pF
× 24 MHz
× 10.9 V
= 0.023 W
Data
64
50
× 14.7 pF
× 24 MHz
× 10.9 V
= 0.123 W
CLKOUT
1
× 4.7 pF
× 48 MHz
× 10.9 V
= 0.003 W
PEXT = 0.237 W
Figure 28. Output Enable/Disable
Figure 29. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 30. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
REFERENCE
SIGNAL
tDIS
OUTPUT STARTS
DRIVING
VOH (MEASURED) – V
VOL (MEASURED) + V
tMEASURED
VOH (MEASURED)
VOL (MEASURED)
2.0V
1.0V
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
tDECAY
tENA
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-21160NCB-TBD | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
| ADSP-21160NCBZ-100 | 功能描述:IC DSP CONTROLLER 32BIT 400-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-21160NCE-100 | 制造商:Analog Devices 功能描述: |
| ADSP-21160NKB-100 | 功能描述:IC DSP CONTROLLER 32BIT 400BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21160NKB-95 | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
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