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参数资料
| 型号： | ADSP-2185BSTZ-133 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100TQFP |
| 标准包装： | 1 |
| 系列： | ADSP-21xx |
| 类型： | 定点 |
| 接口： | 主机接口，串行端口 |
| 时钟速率： | 33.3MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 80kB |
| 电压 - 输入/输出： | 5.00V |
| 电压 - 核心： | 5.00V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
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ADSP-2185
–16–
REV. 0
CAPACITIVE LOADING
Figures 9 and 10 show the capacitive loading characteristics of
the ADSP-2185.
CL – pF
RISE
TIME
(0.4V
–
2.4V
)–
ns
30
300
0
50
100
150
200
250
25
15
10
5
0
20
T = +85
°C
VDD = 4.5V
Figure 9. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
CL – pF
14
0
VALID
OUTPUT
DELAY
OR
HOLD
–
ns
50
100
150
250
200
12
4
2
–2
10
8
NOMINAL
16
18
6
–4
–6
Figure 10. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
tDECAY =
CL × 0.5V
iL
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
1.5V
2.0V
1.5V
0.3V
INPUT
OUTPUT
Figure 11. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
2.0V
1.0V
tENA
REFERENCE
SIGNAL
OUTPUT
tDECAY
VOH
(MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
tDIS
tMEASURED
VOL
(MEASURED)
VOH (MEASURED) – 0.5V
VOL (MEASURED) +0.5V
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
VOH
(MEASURED)
VOL
(MEASURED)
Figure 12. Output Enable/Disable
TO
OUTPUT
PIN
50pF
+1.5V
IOH
IOL
Figure 13. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-2185BSTZ-133 | 制造商:Analog Devices 功能描述:IC 16-BIT MICROCOMPUTER |
| ADSP-2185KST-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,28MHZ,32K WORD RAM, 100TQFP - Bulk |
| ADSP2185KST133 | 制造商:Analog Devices 功能描述: |
| ADSP-2185KST-133 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 33.3MHz 33.3MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:DSP,5V,33MHZ,32K WORD RAM, 100TQFP - Bulk 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
| ADSP-2185KSTZ-115 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 28.8MHz 28.8MIPS 100-Pin LQFP 制造商:Analog Devices 功能描述:MICROCOMPUTER 16BIT 28MIPS SMD |
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