参数资料
型号: ADSP-TS101SAB2-000
厂商: Analog Devices Inc
文件页数: 15/48页
文件大小: 0K
描述: IC DSP CONTROLLER 6MBIT 484 BGA
标准包装: 1
系列: TigerSHARC®
类型: 定点/浮点
接口: 主机接口,连接端口,多处理器
时钟速率: 250MHz
非易失内存: 外部
芯片上RAM: 768kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 484-BFBGA
供应商设备封装: 484-PBGA(19x19)
包装: 托盘
其它名称: ADSP-TS101SAB2000
Rev. C
|
Page 22 of 48
|
May 2009
ADSP-TS101S
For power-up sequencing, power-up reset, and normal reset
(hot reset) timing requirements, refer to Table 26 and Figure 13,
respectively.
Table 19. AC Asynchronous Signal Specifications (All values in this table are in nanoseconds)
Name
Description
Pulse Width Low (min)
Pulse Width High (min)
IRQ3–01
Interrupt request input
tCCLK + 3 ns
DMAR3–01
DMA request input
tCCLK + 4 ns
TMR0E
2
Timer 0 expired output
4
t
SCLK ns
FLAG3–0
Flag pins input
3
t
CCLK ns
3
t
CCLK ns
TRST
JTAG test reset input
1 ns
1 These input pins do not need to be synchronized to a clock reference.
2 This pin is a strap option. During reset, an internal resistor pulls the pin low.
3 For output specifications, see Table 29 and Table 30.
Table 20. Reference Clocks—Core Clock (CCLK) Cycle Time
Parameter
Description
Grade = 100 (300 MHz)
Grade = 000 (250 MHz)
Unit
Min
Max
Min
Max
tCCLK
1
Core Clock Cycle Time
3.3
12.5
4.0
12.5
ns
1 CCLK is the internal processor clock or instruction cycle time. The period of this clock is equal to the system clock period (tSCLK) divided by the system clock ratio
(SCLKRAT2–0). For information on available part numbers for different internal processor clock rates, see the Ordering Guide on Page 45.
Figure 9. Reference Clocks—Core Clock (CCLK) Cycle Time
Table 21. Reference Clocks—Local Clock (LCLK) Cycle Time
Parameter
Description
Min
Max
Unit
tLCLK
1, 2, 3, 4
Local Clock Cycle Time
10
25
ns
tLCLKH
Local Clock Cycle High Time
0.4 × tLCLK
0.6 × tLCLK
ns
tLCLKL
Local Clock Cycle Low Time
0.4 × tLCLK
0.6 × tLCLK
ns
tLCLKJ
5, 6
Local Clock Jitter Tolerance
500
ps
1 For more information, see Table 3 on Page 12.
3 LCLK_P and SCLK_P must be connected to the same source.
4 The value of (tLCLK / LCLKRAT2-0) must not violate the specification for tCCLK.
5 Actual input jitter should be combined with ac specifications for accurate timing analysis.
6 Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
Figure 10. Reference Clocks—Local Clock (LCLK) Cycle Time
CCLK
tCCLK
LCLK_P
tLCLK
tLCLKH
tLCLKL
tLCLKJ
LCLK_P
tLCLK
tLCLKH
tLCLKL
tLCLKJ
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