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参数资料
| 型号： | ADSP-TS203SABPZ050 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 500 MHz TigerSHARC Processor with 4 Mbit on-chip embedded DRAM; Package: 576 ball SBGA; No of Pins: 576; Temperature Range: Ind |
| 中文描述： | 32-BIT, 125 MHz, OTHER DSP, PBGA576 |
| 封装： | 25 X 25 MM, MS-034, BGA-576 |
| 文件页数： | 47/48页 |
| 文件大小： | 2017K |
| 代理商： | ADSP-TS203SABPZ050 |
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Rev. C
|
Page 8 of 48
|
December 2006
ADSP-TS203S
transfer data from an external I/O device to external
SDRAM memory. During a transaction, the DSP relin-
quishes the external data bus; outputs addresses and
memory selects (MSSD3–0); outputs the IORD, IOWR,
IOEN, and RD/WR strobes; and responds to ACK.
DMA chaining. DMA chaining operations enable applica-
tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.
Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
Figure 4. ADSP-TS203S Shared Memory Multiprocessing System
CLKS/REFS
ADDR31–0
DATA31–0
BR1
BR7–2,0
ADDR31–0
DATA31–0
BR0
BR7–1
BMS
CONTROL
ADSP-TS203S #0
CONTROL
ADSP-TS203S #1
ADSP-TS203S #7
ADSP-TS203S #6
ADSP-TS203S #5
ADSP-TS203S #4
ADSP-TS203S #3
ADSP-TS203S #2
RESET
RST_IN
ID2–0
CLKS/REFS
SCLK_VREF
VREF
SCLK
SCLKRAT2–0
000
CLOCK
REFERENCE
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
MS1–0
ACK
ID2–0
001
HBG
HBR
BOFF
BRST
CS
WE
WRL
C
O
N
T
R
O
L
A
D
R
E
S
D
A
T
A
C
O
N
T
R
O
L
A
D
R
E
S
D
A
T
A
SDRAM
MEMORY
(OPTIONAL)
MSSD3–0
IORD
IOEN
RAS
CAS
LDQM
SDWE
SDCKE
SDA10
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
MSH
DMAR3–0
DPA
CPA
LINK
DEVICES
(2 MAX)
(OPTIONAL)
LxCLKINP/N
LxACKO
LxDATI3–0P/N
LxBCMPI
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
TMR0E
BM
CONTROLIMP1–0
LINK
IRQ3–0
FLAG3–0
LINK
RST_IN
BUSLOCK
CLOCK
DS2–0
IOWR
JTAG
POR_IN
RST_OUT
REFERENCE
LINK
DEVICES
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全称:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410S | 功能描述:模数转换器 - ADC 0 to 70C 66-pin DIP Quad 14-Bit, 10MPS RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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