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参数资料
| 型号： | ADSQ-1410-EX-C |
| 厂商： | MURATA POWER SOLUTIONS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, DMA66 |
| 封装： | ROHS COMPLIANT, SMT-66 |
| 文件页数： | 10/11页 |
| 文件大小： | 432K |
| 代理商： | ADSQ-1410-EX-C |
ADSQ-1410
Quad 14-Bit, 10 MSPS Sampling A/D Converter
DATEL
11 Cabot Boulevard, Manseld, MA 02048-1151 USA
Tel: (508) 339-3000
www.datel.com
e-mail: help@datel.com
01 Apr 2011
MDA_ADSQ.B02 Page 8 of 11
Typical Performance Curves and Plots
Dynamic DNL
Fs: 4.85 MHz Fs: 10MHz Range Voltage: 2.5V
Grounded Input Histogram 16384 points
RANGE pin = 1V
Grounded Input Histogram 16384 points
RANGE pin = 2.5V
-0.6
-0.4
-0.2
0
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80%
8193
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8194
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SPECIFICATION DEFINITIONS
Total Harmonic Distortion (THD): Ratio of total RMS harmonic power to
RMS fundamental power
THD = 10 X log (RMS of all harmonics/RMS of fundamental)
SNR With Distortion (SINAD): Ratio of RMS power present in output,
excluding fundamental: to the RMS fundamental power
SINAD = 10 X log (fundamental RMS / RMS of remaining output);
expressed in db
SNR without Distortion (SNR): Ratio of RMS power present in output,
excluding fundamental and harmonics: to the RMS power of the funda-
mental
SNR = 10 X log (fundamental RMS / RMS of power present in output,
excluding fundamental and harmonics, to the fundamental; expressed
in db
Spurious Free Dynamic Range (SFDR): Difference between fundamental
peak value and the value of highest spike present in the output (harmonic
or spur).
SFRD = Fundamental (dB) – Highest Spur (dB) ; expressed in db
PSSR: Survo-loop is employed applying an input voltage that forces
output codes to FS-1LSB. One supply voltage is changed to the specied
limits and any change in input voltage recorded. The change in input volt-
age is divided by the full scale voltage and then divided by percent change
in power supplies. The resulting units are % / %.
Zero Error: Survo-loop is employed applying an input voltage that forces
output codes to:
Unipolar devices - LSB on half of the time and all other bits off.
Bipolar devices - MSB on, the LSB on half the time and all other bits off.
The input voltage is compared to 0V.
The result is = Input voltage - 0.5 LSB.
Offset Error: Survo-loop is employed applying an input voltage that forces
output codes to LSB on half of the time, and all other bits off.
The input voltage is compared to 0V for unipolar devices, and -0.5 X full
scale for bipolar devices. The result is this difference - 0.5 LSBs.
Full Scale Absolute Accuracy: Survo-loop is employed applying an input
voltage that forces output codes to LSB on half of the time and all other bits
on. The input voltage is compared to full scale for unipolar devices, and 0.5
X full scale for bipolar devices. The result is this difference + 1.5 LSBs.
Gain Error: The result is the difference between the Offset Error result and
the Full Scale Absolute Accuracy result.
Dynamic DNL Min: An AC signal is input to the device. 2n x 128 (2.1e6 for
14 bit converter) samples are taken, and the number of times each code
appears is recorded. The data is normalized using ideal sine wave values.
The result is the most negative and most positive numbers in the array.
Grounded Input RMS Noise: Input to the device is tied to Signal Ground.
2n x 128 (2.1e6 for 14 bit converter) samples are taken and stored in an
array. The result is the RMS value of this array.
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