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参数资料
| 型号： | ADT7463ARQZ-REEL7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 13/50页 |
| 文件大小： | 726K |
| 描述： | IC REMOTE THERMAL CTRLR 24-QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 500 |
| 系列： | dBCool® |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 120°C，外部传感器 |
| 精确度： | ±1.5°C（最小值） |
| 拓扑： | ADC，比较器，风扇速度计数器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 120°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 24-QSOP |
| 包装： | 带卷 (TR) |
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ADT7463
http://onsemi.com
13
Figure 19. Reading Data from a Previously Selected Register
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK. BY
MASTER
START BY
MASTER
9
1
ACK. BY
ADT7463
9
STOP BY
MASTER
1
A1
A0
1
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADT7463
R/W
1
0
1
0
When reading data from a register, there are two
possibilities:
1. If the ADT7463s address pointer register value is
unknown or not the desired value, it is first
necessary to set it to the correct value before data
can be read from the desired data register. This is
done by performing a write to the ADT7463 as
before, however, only the data byte is sent and this
contains the register address. This is shown in
Figure 18.
A read operation is then performed consisting of
the serial bus address, R/W
bit set to 1, followed
by the data byte read from the data register. This is
shown in Figure 19.
2. If the address pointer register is already at the
desired address, data can be read from the
corresponding data register without first writing to
the address pointer register, so Figure 18 can be
omitted.
NOTES:
1. It is possible to read a data byte from a data register without
first writing to the address pointer register if the address
pointer register is already at the correct value. However, it
is not possible to write data to a register without writing to the
address pointer register because the first data byte of a write
is always written to the address pointer register.
2. In Figures 17 to 19, the serial bus address is shown as the
default value 01011(A1)(A0), where A1 and A0 are set by
the address select mode function previously defined.
3. In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7463 also supports the Read Byte
protocol (see System Management Bus specifications Rev.
2.0 for more information).
4. If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
ADT7463 Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7463 are discussed below. The following
abbreviations are used in the diagrams:
S START
P STOP
R READ
W WRITE
A ACKNOWLEDGE
A
NO ACKNOWLEDGE
The ADT7463 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on SDA
2. The master sends the 7bit slave address followed
by the write bit (low)
3. The addressed slave device asserts ACK on SDA
4. The master sends a command code
5. The slave asserts ACK on SDA
6. The master asserts a stop condition on SDA and
the transaction ends
For the ADT7463, the send byte protocol is used to write
a register address to RAM for a subsequent single byte read
from the same address. This is illustrated in Figure 20.
Figure 20. Setting a Register Address for
Subsequent Read
SLAVE
ADDRESS
W A
S
A P
REGISTER
ADDRESS
2
3
1
5 6
4
If it is required to read data from the register immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry
out a single byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA
2. The master sends the 7bit slave address followed
by the write bit (low)
3. The addressed slave device asserts ACK on SDA
4. The master sends a command code
5. The slave asserts ACK on SDA
6. The master sends a data byte
7. The slave asserts ACK on SDA
8. The master asserts a stop condition on SDA to end
the transaction
This is illustrated in Figure 21.
Figure 21. Single Byte Write to a Register
SLAVE
ADDRESS
W A
DATA
S
A
A P
REGISTER
ADDRESS
2
3
1
5
6
7 8
4
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