参数资料
型号: ADT7467ARQ-REEL7
厂商: ON Semiconductor
文件页数: 9/72页
文件大小: 0K
描述: IC REMOTE THERMAL CTRLR 16-QSOP
产品变化通告: MFG CHG Notification ADI to ON Semi
Product Obsolescence 11/Feb/2009
标准包装: 1,000
系列: dBCool®
功能: 风扇控制,温度监控器
传感器类型: 内部和外部
感应温度: -40°C ~ 120°C,外部传感器
精确度: ±1.5°C
拓扑: ADC,比较器,风扇速度计数器,多路复用器,寄存器库
输出类型: SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 120°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
ADT7467
Bit 2 sets the direction for the GPIO: 0 = input, 1 = output.
Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high.
Setting the Functionality of Pin 9
Pin 9 on the ADT7467 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user
chooses the required functionality by setting Bit 0 and Bit 1
of Configuration Register 4 at Address 0x7D.
Recommended Implementation
Configuring the ADT7467 as in Figure NO TAG allows
the system designer to use the following features:
? Two PWM Outputs for Fan Control of Up to Three
Fans (The Front and Rear Chassis Fans are Connected in
Parallel)
? Three TACH Fan Speed Measurement Inputs
? V CC Measured Internally through Pin 3
Table 4. PIN 9 SETTINGS
Bit 1 Bit 0
0 0
0 1
1 0
Function
TACH4
THERM
SMBALERT
? CPU Temperature Measured Using the Remote 1
Temperature Channel
? Ambient Temperature Measured through the Remote 2
Temperature Channel
? Bidirectional THERM Pin. This Feature Allows Intel ?
Pentium ? 4 PROCHOT Monitoring and Can Function as
1
1
GPIO
an Overtemperature THERM Output. Alternatively, it
Can be Programmed as an SMBALERT System Interrupt
Output
FRONT
CHASSIS
FAN
ADT7467
PWM1
TACH2
TACH1
CPU FAN
REAR
CHASSIS
FAN
PWM3
TACH3
D2+
D2 ?
THERM
PROCHOT
CPU
AMBIENT
TEMPERATURE
D1+
D1 ?
SDA
SCL
SMBALERT
GND
ICH
Figure 14. ADT7467 Implementation
Serial Bus Interface
On PCs and servers, control of the ADT7467 is carried out
using the serial system management bus (SMBus). The
ADT7467 is connected to this bus as a slave device under the
control of a master controller, which is usually (but not
necessarily) the ICH.
The ADT7467 has a fixed 7-bit serial bus address of
0101110 or 0x2E. The read/write bit must be added to get the
8-bit address (01011100 or 0x5C). Data is sent over the serial
bus in sequences of nine clock pulses: eight bits of data
followed by an acknowledge bit from the slave device.
Transitions on the data line must occur during the low period
of the clock signal and remain stable during the high period,
because a low-to-high transition might be interpreted as a
stop signal when the clock is high. The number of data bytes
that can be transmitted over the serial bus in a single read or
write operation is only limited by what the master and slave
devices can handle.
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device overrides the
acknowledge bit by pulling the data line high during the low
period before the ninth clock pulse. This is known as a no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, and then high
during the 10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the
serial bus in one operation. It is not possible to mix a read and
a write in one operation, however, because the type of
operation is determined at the beginning and cannot
subsequently be changed without starting a new operation.
http://onsemi.com
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