参数资料
型号: ADT7468ARQ
厂商: ON Semiconductor
文件页数: 46/81页
文件大小: 0K
描述: IC REMOTE THERMAL CTRLR 24-QSOP
产品变化通告: MFG CHG Notification ADI to ON Semi
Product Obsolescence 11/Feb/2009
标准包装: 56
系列: dBCool®
功能: 风扇控制,温度监控器
传感器类型: 内部和外部
感应温度: -40°C ~ 120°C,外部传感器
精确度: ±2°C(最小值)
拓扑: ADC,比较器,风扇速度计数器,多路复用器,寄存器库
输出类型: SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 120°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: 24-QSOP
包装: 管件
ADT7468
STEP 4: PWM MIN FOR EACH PWM (FAN) OUTPUT
PWM MIN is the minimum PWM duty cycle at which each fan in
the system runs. It is also the start speed for each fan under
automatic fan control once the temperature rises above T MIN .
For maximum system acoustic benefit, PWM MIN should be as
low as possible. Depending on the fan used, the PWM MIN
setting is usually in the 20% to 33% duty cycle range. This value
can be found through fan validation.
Programming the PWM MIN Registers
The PWM MIN registers are 8-bit registers that allow the mini-
mum PWM duty cycle for each output to be configured
anywhere from 0% to 100%. This allows the minimum PWM
duty cycle to be set in steps of 0.39%.
The value to be programmed into the PWM MIN register is given
by
Value (decimal) = PWM MIN /0.39
100%
Example 1: For a minimum PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 80 (hex)
PWM MIN
Example 2: For a minimum PWM duty cycle of 33%,
0%
Value (decimal) = 33/0.39 = 85 (decimal)
T MIN
TEMPERATURE
Value = 85 (decimal)l or 54 (hex)
Figure 59. PWM MIN Determines Minimum PWM Duty Cycle
More than one PWM output can be controlled from a single
temperature measurement channel. For example, Remote 1
temperature can control PWM1 and PWM2 outputs. If two
different fans are used on PWM1 and PWM2, then the fan
characteristics can be set up differently. As a result, Fan 1 driven
by PWM1 can have a different PWM MIN value than that of Fan 2
connected to PWM2. Figure 60 illustrates this as PWM1 MIN
(front fan) is turned on at a minimum duty cycle of 20%, while
PWM2 MIN (rear fan) turns on at a minimum of 40% duty cycle.
Note, however, that both fans turn on at exactly the same
temperature, defined by T MIN .
100%
PWM MIN Registers
Reg. 0x64, PWM1 minimum duty cycle = 0x80 (50% default)
Reg. 0x65 PWM2 minimum duty cycle = 0x80 (50% default)
Reg. 0x66, PWM3 minimum duty cycle = 0x80 (50% default)
Note on Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in
RPM. Running a fan at 33% PWM duty cycle does not equate to
running the fan at 33% speed. Driving a fan at 33% PWM duty
cycle actually runs the fan at closer to 50% of its full speed. This
is because fan speed in %RPM generally relates to the square
root of PWM duty cycle. Given a PWM square wave as the
drive signal, fan speed in RPM approximates to
PW
M2
% fanspeed = PWM duty cycle × 10
PWM2 MIN
PWM1 MIN
0%
PW
M1
STEP 5: PWM MAX FOR PWM (FAN) OUTPUTS
PWM MAX is the maximum duty cycle that each fan in the system
runs at under the automatic fan speed control loop. For
maximum system acoustic benefit, PWM MAX should be as low
T MIN
TEMPERATURE
as possible, but should be capable of maintaining the processor
Figure 60. Operating Two Different Fans from a Single Temperature Channel
temperature limit at an acceptable level. If the THERM
temperature limit is exceeded, the fans are still boosted to 100%
for fail-safe cooling.
There is a PWM MAX limit for each fan channel. The default value
of this register is 0xFF and so has no effect unless it is
programmed.
Rev. 3 | Page 46 of 81 | www.onsemi.com
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