参数资料
| 型号： | ADT7473ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 66/73页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADT7473 |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 1 |
| 系列： | dBCool® |
| 类型： | 温度传感器 |
| 适用于相关产品： | ADT7473 |
| 所含物品： | 评估板 |
| 其它名称： | EVAL-ADT7473EBZ EVAL-ADT7473EBZ-ND |
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ADT7473
Table 74. Register 0x63 ? Enhanced Acoustics Register 2 (Power-On Default = 0x00)
Bit No.
<2:0>
Mnemonic
ACOU3
R/W (Note 1)
R/W
Description
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping
instantly to its newly calculated speed, PWM3 ramps gradually at the rate determined by
these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase Time for 33% to 100%
000 = 1
001 = 2
010 = 3
011 = 4
100 = 8
101 = 12
110 = 24
111 = 48
35 sec
17.6 sec
11.8 sec
7.0 sec
4.4 sec
3.0 sec
1.6 sec
0.8 sec
<3>
<6:4>
EN3
ACOU2
R/W
R/W
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping
instantly to its newly calculated speed, PWM2 ramps gradually at the rate determined by
these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase Time for 33% to 100%
000 = 1
001 = 2
010 = 3
011 = 4
100 = 8
101 = 12
110 = 24
111 = 48
35 sec
17.6 sec
11.8 sec
7.0 sec
4.4 sec
3.0 sec
1.6 sec
0.8 sec
<7>
EN2
R/W
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any further attempts to write to this register have
no effect.
Table 75. PWM MINIMUM DUTY CYCLE REGISTERS
Register Address
0x64
0x65
0x66
R/W (Note 1)
R/W
R/W
R/W
Description
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
Power-On Default
0x80 (50% Duty Cycle)
0x80 (50% Duty Cycle)
0x80 (50% Duty Cycle)
1. These registers become read-only when the Configuration Register 1 Lock bit is set. Any further attempts to write to these registers have
no effect.
Table 76. REGISTER 0X64, REGISTER 0X65, AND REGISTER 0X66 - PWM MINIMUM DUTY CYCLE REGISTERS
(POWER-ON DEFAULT = 0X80, 50% DUTY CYCLE)
Bit No.
<7:0>
Mnemonic
PWM Duty Cycle
R/W
R/W
Description
These bits define the PWM MIN duty cycle for PWMx.
0x00 = 0% Duty Cycle (Fan Off)
0x40 = 25% Duty Cycle
0x80 = 50% Duty Cycle
0xFF = 100% Duty Cycle (Fan Full Speed)
Table 77. T MIN REGISTERS (Note 1)
Register Address
0x67
0x68
0x69
R/W (Note 2)
R/W
R/W
R/W
Description
Remote 1 Temperature T MIN
Local Temperature T MIN
Remote 2 Temperature T MIN
Power-On Default
0x9A (90 ? C)
0x9A (90 ? C)
0x9A (90 ? C)
1. These are the T MIN registers for each temperature channel. When the temperature measured exceeds T MIN , the appropriate fan runs at
minimum speed and increases with temperature according to T RANGE .
2. These registers become read-only when the Configuration Register 1 Lock bit is set. Any further attempts to write to these registers have
no effect.
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