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参数资料
| 型号： | ADT7475ARQZ-RL7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/58页 |
| 文件大小： | 0K |
| 描述： | IC REMOTE THERMAL CTLR 16QSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Discontinuation 30/Sept/2011 |
| 标准包装： | 1,000 |
| 系列： | dBCool® |
| 功能： | 风扇控制，温度监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | -40°C ~ 125°C，外部传感器 |
| 精确度： | ±1.5°C（最小值） |
| 拓扑： | ADC，比较器，风扇速度计数器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 带卷 (TR) |
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ADT7475
If the THERM timer value exceeds the THERM timer
limit value, then the F4P bit (Bit 5) of Interrupt Status
Register 2 is set, and an SMBALERT is generated. Note that
the F4P bit (Bit 5) of Interrupt Mask Register 2 (0x75)
masks out SMBALERTs if this bit is set to 1, although the
F4P bit of Interrupt Status Register 2 is still set if the
THERM timer limit is exceeded.
Figure 28 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes
SMBALERT to be generated on the first THERM assertion. A
THERM timer limit value of 0x01 generates an SMBALERT
once cumulative THERM assertions exceed 45.52 ms.
Configuring the THERM Behavior
1. Configure the relevant pin as the THERM timer
input. Setting Bit 1 (THERM) of Configuration
Register 3 (0x78) enables the THERM timer
monitoring functionality. This is disabled on Pin 9
by default.
Setting Bit 0 and Bit 1 (PIN9FUNC) of
Configuration Register 4 (0x7D) enables THERM
timer/output functionality on Pin 9 (Bit 1,
THERM, of Configuration Register 3, must also
be set). Pin 9 can also be used as TACH4.
2. Select the desired fan behavior for THERM timer
events.
Assuming that the fans are running, setting Bit 2
(BOOST bit) of Configuration Register 3 (0x78)
causes all fans to run at 100% duty cycle whenever
THERM is asserted. This allows fail-safe system
cooling. If this bit is 0, the fans run at their current
settings and are not affected by THERM events. If
the fans are not already running when THERM is
asserted, the fans do not run to full speed.
3. Select whether THERM timer events should
generate SMBALERT interrupts.
Bit 5 (F4P) of Interrupt Mask Register 2 (0x75),
when set , masks out SMBALERTs when the
THERM timer limit value is exceeded. This bit
should be cleared if SMBALERTs based on
THERM events are required.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is
generated on the first THERM assertion or only if
a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes a n SMBALERT
to be generated on the first THERM assertion.
5. Select a THERM monitoring time.
This value specifies how often OS- or BIOS-level
software checks the THERM timer. For example,
BIOS could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>2.914 s in Hour 3, this can indicate that system
performance is degrading significantly because
THERM is asserting more frequently on an hourly
basis.
Alternatively, OS- or BIOS-level software can
time-stamp when the system is powered on. If an
SMBALERT is generated due to the THERM timer
limit being exceeded, another time-stamp can be
taken. The difference in time can be calculated for a
fixed THERM timer limit time. For example, if it
takes one week for a THERM timer limit of
2.914 seconds to be exceeded and the next time it
takes only one hour, this is an indication of a
serious degradation in system performance.
Configuring the THERM Pin as an Output
In addition to monitoring THER M as an input, the
ADT7475 can optionally drive THERM low as an output. In
cases where PROCHOT is bidirectional, THERM can be
used to throttle the processor by asserting PROCHOT. The
user can pre-program system-critical thermal limits. If the
temperature exceeds a thermal limit by 0.25 ° C, THERM
asserts low. If the temperature is still above the thermal limit
on the next monitoring cycle, THERM stays low. THERM
remains asserted low until the temperature is equal to or
below the thermal limit. Because the temperature for that
channel is measured only once for every monitoring cycle,
after THERM asserts, it is guaranteed to remain low for at
least one monitoring cycle.
The THERM pin can be configured to assert low if the
Remote 1, local, or Remote 2 THERM temperature limit is
exceeded by 0.25 ° C. The THERM temperature limit
registers are at Register 0x6A, Register 0x6B, and
Register 0x6C. Setting Bit 3 of Register 0x5F,
Register 0x60, and Register 0x61 enables the THERM
output feature for the Remote 1, local, and Remote 2
temperature channels, respectively. Figure 29 shows how
the THERM pin asserts low as an output in the event of a
critical over temperature.
THERM LIMIT
0.25 5 C
THERM LIMIT
TEMP
THERM
MONITORING
CYCLE
Figure 29. Asserting THERM as an Output, Based on
Tripping THERM Limits
An alternative method of disabling THERM is to program
the THERM temperature limit to 64 ° C or less in Offset 64
mode, or 128 ° C or less in twos complement mode; that is, for
THERM temperature limit values less than 64 ° C or 128 ° C,
respectively, THERM is disabled.
http://onsemi.com
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