ADT7481
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13
Table 16. LIST OF REGISTERS (continued)
Read
Address
(Hex)
Lock
Comment
Power-On Default
Mnemonic
Write
Address
(Hex)
19
19
Remote 2 THERM
Limit
0101 0101 (0x55) (85癈)
Bit 3 Conf Reg = 1
Yes
20
20
Local THERM
Limit
0101 0101 (0x55) (85癈)
Yes
21
21
THERM
Hysteresis
0000 1010 (0x0A) (10癈)
Yes
22
22
Consecutive ALERT
0000 0001 (0x01)
Yes
23
N/A
Status Register 2
0000 0000 (0x00)
No
24
24
Configuration 2 Register
0000 0000 (0x00)
Yes
30
N/A
Remote 2 Temperature Value High Byte
0000 0000 (0x00)
No
31
31
Remote 2 Temp High Limit High Byte
0101 0101 (0x55) (85癈)
Yes
32
32
Remote 2 Temp Low Limit High Byte
0000 0000 (0x00) (0癈)
Yes
33
N/A
Remote 2 Temperature Value Low Byte
0000 0000 (0x00)
No
34
34
Remote 2 Temperature Offset High Byte
0000 0000 (0x00)
Yes
35
35
Remote 2 Temperature Offset Low Byte
0000 0000 (0x00)
Yes
36
36
Remote 2 Temp High Limit Low Byte
0000 0000 (0x00) (0癈)
Yes
37
37
Remote 2 Temp Low Limit Low Byte
0000 0000 (0x00) (0癈)
Yes
39
39
Remote 2 THERM
Limit
0101 0101 (0x55) (85癈)
Yes
3D
N/A
Device ID
1000 0001 (0x81)
3E
N/A
Manufacturer ID
0100 0001 (0x41)
N/A
1.  Writing to Address 0F causes the ADT7481 to perform a single measurement. It is not a data register as such, and it does not matter what
data is written to it.
Serial Bus Interface
Control of the ADT7481 is achieved via the serial bus.
The ADT7481 is connected to this bus as a slave device
under the control of a master device.
The ADT7481 has an SMBus timeout feature. When this
is enabled, the SMBus will typically timeout after 25 ms of
no activity. However, this feature is not enabled by default.
Set Bit 7 (SCL timeout bit) of the consecutive alert register
(Address 0x22) to enable the SCL timeout. Set Bit 6 (SDA
timeout bit) of the consecutive alert register (Address 0x22)
to enable the SDA timeout.
The ADT7481 supports packet error checking (PEC) and
its use is optional. It is triggered by supplying the extra clock
for the PEC byte. The PEC byte is calculated using CRC8.
The frame check sequence (FCS) conforms to CRC8 by the
polynomial:
C(x) + x
8
) x
2
) x
1
) 1
(eq. 1)
Consult   the   SMBus 1.1   specification   for   more
information (www.smbus.org
).
Addressing the Device
In general, every SMBus device has a 7-bit device
address, except for some devices that have extended, 10-bit
addresses. When the master device sends a device address
over the bus, the slave device with that address responds.
The ADT7481 is available with one device address, 0x4C
(1001 100b). An ADT74811 is also available. The only
difference between the ADT7481 and the ADT74811 is the
SMBus address. The ADT74811 has a fixed SMBus
address of 0x4B (1001 011b). The addresses mentioned in
this datasheet are 7-bit addresses. The R/W
bit needs to be
added to arrive at an 8-bit address. Other than the different
SMBus addresses, the ADT7481 and the ADT74811 are
functionally identical.
The serial bus protocol operates as follows:
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line (SDATA) while the serial clock line (SCLK)
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus a R/W
bit,
which determines the direction of the data transfer, that is,
whether data will be written to, or read from, the slave
device. The peripheral with the address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known as
the acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W
bit is 0, the master writes to the slave
device. If the R/W
bit is 1, the master reads from the slave
device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high may be interpreted as a stop signal.