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| 型号： | ADUM1100AR-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL ISOL/COUPLER 8SOIC |
| 产品培训模块： | Power Line Monitoring |
| 设计资源： | USB Cable Isolator Circuit (CN0159) |
| 其它图纸： | ADUM Single Channel |
| 标准包装： | 1 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 1/0 |
| 通道数： | 1 |
| 电源电压： | 3 V ~ 5.5 V |
| 电压 - 隔离： | 2500Vrms |
| 数据速率： | 25Mbps |
| 传输延迟： | 10.5ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 标准包装 |
| 工作温度： | -40°C ~ 105°C |
| 其它名称： | ADUM1100AR-RL7DKR |
Data Sheet
ADuM1100
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Pulse Width Distortion, |t PLH ? t PHL | 5
PWD
5 V/3 V Operation
3 V/5 V Operation
0.5
0.5
2
3
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Change in Pulse Width Distortion vs.
Temperature 6
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
t PSK1
3
10
ps/°C
ps/°C
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Temperature) 5, 7
5 V/3 V Operation
3 V/5 V Operation
Propagation Delay Skew (Equal
t PSK2
12
15
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Temperature, Supplies) 5, 7
5 V/3 V Operation
3 V/5 V Operation
9
12
ns
ns
C L = 15 pF, CMOS signal levels
C L = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
t R , t F
3
ns
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
|CM L |,
25
35
kV/μs
V I = 0 V or V DD1 , V CM = 1000 V,
Logic Low/High Output 8
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Dynamic Supply Current 9
5 V/3 V Operation
3 V/5 V Operation
Output Dynamic Supply Current 9
5 V/3 V Operation
3 V/5 V Operation
|CM H |
f r
C PD1
C PD2
1.2
1.1
0.09
0.08
0.04
0.02
Mbps
Mbps
mA/Mbps
mA/Mbps
mA/Mbps
mA/Mbps
transient magnitude = 800 V
1
2
3
4
5
6
7
8
9
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t PHL is measured from the 50% level of the falling edge of the V I signal to the 50% level of the falling edge of the V O signal. t PLH is measured from the 50% level of the
rising edge of the V I signal to the 50% level of the rising edge of the V O signal.
Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width
distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.
Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
t PSK1 is the magnitude of the worst-case difference in t PHL and/or t PLH that is measured between units at the same operating temperature and output load within the
recommended operating conditions. t PSK2 is the magnitude of the worst-case difference in t PHL and/or t PLH that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2 . CM L is the maximum common-mode voltage slew rate
that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
Rev. I | Page 9 of 20
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