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参数资料
| 型号： | ADUM1250SRZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/16页 |
| 文件大小： | 0K |
| 描述： | IC ISOLATOR 1MBPS 4CH 2.5K 8SOIC |
| 标准包装： | 1,000 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 2/2 |
| 通道数： | 4 |
| 电源电压： | 3 V ~ 5.5 V |
| 电压 - 隔离： | 2500Vrms |
| 数据速率： | 1Mbps |
| 传输延迟： | 150ns |
| 输出类型： | I²C? |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 125°C |
ADuM1250/ADuM1251
Data Sheet
AC Specifications 1
All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications
are at T A = 25°C, V DD1 = 3.3 V or 5 V, and V DD2 = 3.3 V or 5 V, unless otherwise noted. Refer to Figure 5.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
1000
kHz
4.5 V ≤ V DD1 , V DD2 ≤ 5.5 V, C L1 = 40 pF,
R1 = 1.6 kΩ, C L2 = 400 pF, R2 = 180 Ω
Side 1 Output (0.9 V DD1 to 0.9 V)
Side 2 Output (0.9 V DD2 to 0.1 V DD2 )
t f1
t f2
13
32
26
52
120
120
ns
ns
3 V Operation
3.0 V ≤ V DD1 , V DD2 ≤ 3.6 V, C L1 = 40 pF,
R1 = 1.0 kΩ, C L2 = 400 pF, R2 = 120 Ω
Side 1 Output (0.9 V DD1 to 0.9 V)
Side 2 Output (0.9 V DD2 to 0.1 V DD2 )
t f1
t f2
13
32
32
61
120
120
ns
ns
PROPAGATION DELAY
5 V Operation
4.5 ≤ V DD1 , V DD2 ≤ 5.5 V, C L1 = C L2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, Rising Edge 2
Side 1-to-Side 2, Falling Edge 3
Side 2-to-Side 1, Rising Edge 4
Side 2-to-Side 1, Falling Edge 5
t PLH12
t PHL12
t PLH21
t PHL21
95
162
31
85
130
275
70
155
ns
ns
ns
ns
3 V Operation
3.0 V ≤ V DD1 , V DD2 ≤ 3.6 V, C L1 = C L2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, Rising Edge 2
Side 1-to-Side 2, Falling Edge 3
Side 2-to-Side 1, Rising Edge 4
Side 2-to-Side 1, Falling Edge 5
t PLH12
t PHL12
t PLH21
t PHL21
82
196
32
110
125
340
75
210
ns
ns
ns
ns
PULSE WIDTH DISTORTION
5 V Operation
4.5 V ≤ V DD1 , V DD2 ≤ 5.5 V, C L1 = C L2 = 0 pF,
R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, |t PLH12 ? t PHL12 |
Side 2-to-Side 1, |t PLH21 ? t PHL21 |
PWD 12
PWD 21
67
54
145
85
ns
ns
3 V Operation
3.0 V ≤ V DD1 , V DD2 ≤ 3.6 V, C L1 = C L2 = 0 pF,
R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, |t PLH12 ? t PHL12 |
Side 2-to-Side 1, |t PLH21 ? t PHL21 |
PWD 12
PWD 21
114
77
215
135
ns
ns
COMMON-MODE TRANSIENT IMMUNITY 6
|CM H |, |CM L |
25
35
kV/μs
1
2
3
4
5
6
All voltages are relative to their respective ground.
t PLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 V DD2 .
t PHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
t PLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 V DD1 .
t PHL21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2 . CM L is the maximum common-mode voltage slew rate
that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Rev. G | Page 4 of 16
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