Data Sheet

ADuM1280/ADuM1281/ADuM1285/ADuM1286

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OPERATION (A, B, AND C GRADES)

All typical specifications are at T A = 25°C, V DD1 = 5 V, V DD2 = 3.0 V. Minimum/maximum specifications apply over the entire recommended

operation range: 4.5 V ≤ V DD1 ≤ 5.5 V, 2.7 V ≤ V DD2 ≤ 3.6 V; and ?40°C ≤ T A ≤ 125°C, unless otherwise noted. Switching specifications are

tested with C L = 15 pF and CMOS signal levels unless otherwise noted.

Table 7.

A Grade

B Grade

C Grade

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Test Conditions

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate

PW

1000

1

40

25

10

100

ns

Mbps

Within PWD limit

Within PWD limit

Propagation Delay

Pulse Width Distortion

t PHL , t PLH

PWD

50

10

35

3

13

20

26

2

ns

ns

50% input to 50% output

|t PLH ? t PHL |

Change vs. Temperature

7

3

1.5

ps/?C

Propagation Delay Skew

t PSK

38

16

12

ns

Between any two units at

same operating conditions

Channel Matching

Codirectional

Opposing-Direction

Jitter

t PSKCD

t PSKOD

2

5

10

2

3

6

1

2

5

ns

ns

ns

7 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

Table 8.

1 Mbps–A, B, C Grade

25 Mbps–B, C Grade

100 Mbps–C Grade

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Test Conditions

SUPPLY CURRENT

No load

ADuM1280 / ADuM1285

ADuM1281 / ADuM1286

I DD1

I DD2

I DD1

I DD2

1.1

2.0

2.1

1.7

1.6

3.5

2.6

2.3

6.2

2.7

4.9

3.9

7.0

4.6

6.0

6.2

20

4.8

15

11

25

9.0

19

15

mA

mA

mA

mA

Table 9. For All Models

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions

DC SPECIFICATIONS

Logic High Input Threshold

Logic Low Input Threshold

V IH

V IL

0.7 V DDx

0.3 V DDx

V

V

Logic High Output Voltages

V OH

V DDx ? 0.1

V DDx ? 0.4

V DDx

V DDx ? 0.2

V

V

I Ox = ?20 μA, V Ix = V IxH

I Ox = ?4 mA, V Ix = V IxH

Logic Low Output Voltages

V OL

0.0

0.2

0.1

0.4

V

V

I Ox = 20 μA, V Ix = V IxL

I Ox = 4 mA, V Ix = V IxL

Input Current per Channel

I I

?10

+0.01

+10

μA

0 V ≤ V Ix ≤ V DDx

Supply Current per Channel

Quiescent Input Supply Current

Quiescent Output Supply Current

Dynamic Input Supply Current

Dynamic Output Supply Current

I DDI(Q)

I DDO(Q)

I DDI(D)

I DDO(D)

0.54

1.2

0.09

0.02

0.75

2.0

mA

mA

mA/Mbps

mA/Mbps

Undervoltage Lockout

Positive V DDX Threshold

Negative V DDX Threshold

V DDX Hysteresis

V DDxUV+

V DDxUV?

V DDxUVH

2.6

2.4

0.2

V

V

V

AC SPECIFICATIONS

Output Rise/Fall Time

t R /t F

2.5

ns

10% to 90%

Common-Mode Transient Immunity 1

Refresh Period

|CM|

t r

25

35

1.6

kV/μs

μs

V Ix = V DDx , V CM = 1000 V,

transient magnitude = 800 V

1

|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining V o > 0.8 V DDX . The common-mode voltage slew rates apply to both

rising and falling common-mode voltage edges.

Rev. B | Page 5 of 20