参数资料
型号: ADUM1310ARWZ-RL
厂商: Analog Devices Inc
文件页数: 4/24页
文件大小: 0K
描述: IC ISOLATOR DGTL 3CHAN 16-SOIC
标准包装: 1,000
系列: iCoupler®
输入 - 1 侧/2 侧: 3/0
通道数: 3
电源电压: 2.7 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 1Mbps
传输延迟: 100ns
输出类型: 逻辑
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
工作温度: -40°C ~ 105°C
其它名称: ADUM1310ARWZ-RL-ND
ADUM1310ARWZ-RLTR
ADuM1310/ADuM1311
Data Sheet
Parameter
Channel-to-Channel Matching,
Symbol
t PSKCD
Min
Typ
Max
5
Unit
ns
Test Conditions
C L = 15 pF, CMOS signal levels
Codirectional Channels 6
Channel-to-Channel Matching,
t PSKOD
6
ns
C L = 15 pF, CMOS signal levels
Opposing-Directional Channels 6
For All Models
Output Rise/Fall Time (10% to 90%)
t R /t F
2.5
ns
C L = 15 pF, CMOS signal levels
Common-Mode Transient Immunity
|CM H |
25
35
kV/μs
V Ix = V DD1 or V DD2 , V CM = 1000 V,
at Logic High Output 7
transient magnitude = 800 V
Common-Mode Transient Immunity
|CM L |
25
35
kV/μs
V Ix = 0 V, V CM = 1000 V,
at Logic Low Output 7
transient magnitude = 800 V
Refresh Rate
f r
1.2
Mbps
Input Enable Time 8
Input Disable Time 8
t ENABLE
t DISABLE
2.0
5.0
μs
μs
V IA , V IB , V IC = 0 V or V DD1
V IA , V IB , V IC = 0 V or V DD1
Input Supply Current per Channel,
I DDI (Q)
0.50
0.73
mA
Quiescent 9
Output Supply Current per Channel,
I DDO (Q)
0.38
0.53
mA
Quiescent 9
Input Dynamic Supply Current
per Channel 10
Output Dynamic Supply Current per
Channel 10
I DDI (D)
I DDO (D)
0.12
0.04
mA/
Mbps
mA/
Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is
t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2 . CM L is the maximum common-mode voltage slew rate
Input enable time is the duration from when V DISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
I DDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
1
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V DD1 and V DD2 supply currents as a function of data rate for ADuM1310 / ADuM1311 channel configurations.
2
3
4
measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.
5
within the recommended operating conditions.
6
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V DISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL 2 logic state (see Table 13).
9
the same orientation as Channel A must be included to account for the total current consumed.
10
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. I | Page 4 of 24
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