参数资料
型号: ADUM1420BRWZ
厂商: Analog Devices Inc
文件页数: 3/12页
文件大小: 0K
描述: IC ISOLATOR DGTL 4CH 28SOIC
产品变化通告: ADuM1420 Obsolescence 09/Mar/2012
其它图纸: ADUM1420 Block Diagram
标准包装: 27
系列: iCoupler®
输入 - 1 侧/2 侧: 4/0
通道数: 4
电源电压: 4.5 V ~ 5.5 V
电压 - 隔离: 1667Vrms
数据速率: 10Mbps
传输延迟: 110ns
输出类型: 逻辑
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC W
包装: 管件
工作温度: -40°C ~ 105°C
产品目录页面: 2766 (CN2011-ZH PDF)

ADuM1420
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
All voltages are relative to their respective ground. 4.5 V ≤ V DD1 ≤ 5.5 V, 12 V ≤ V DDA ≤ 18 V, 12 V ≤ V DDB ≤ 18 V, 12 V ≤ V DDC ≤ 18 V,
12 V ≤ V DDD ≤ 18 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted.
All typical specifications are at T A = 25°C, V DD1 = 5 V, V DDA = 15 V, V DDB = 15 V.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
Output Supply Current (A, B, C, or D), Quiescent
I DDI (Q)
I DDA (Q) , I DDB (Q) ,
5.1
0.3
8.0
1.2
mA
mA
I DDC (Q) , I DDD (Q)
Input Supply Current, 10 Mbps
I DDI (10)
12
16
mA
Output Supply Current (A, B, C, or D), 10 Mbps
I DDA (10) , I DDB (10) ,
16
22
mA
C L = 200 pF
I DDC (10) , I DDD (10)
Input Currents
I IA , I IB , I IC ,
?10
+0.01
+10
μA
0 V ≤ V IA , V IB , V IC , V ID ,
I ID , I DISABLE
V DISABLE ≤ V DD1
Logic High Input Threshold
Logic Low Input Threshold
V IH
V IL
2.0
0.8
V
V
Logic High Output Voltages
V OAH , V OBH ,
V DDA ? 0.1,
V DDA , V DDB ,
V
I OA , I OB , I OC , I OD = ?1 mA
V OCH , V ODH
V DDB ? 0.1,
V DDC ? 0.1,
V DDD ? 0.1
V DDC , V DDD
Logic Low Output Voltages
V OAL , V OBL ,
0.1
V
I OA , I OB , I OC , I OD = 1 mA
V OCL , V ODL
Output Short-Circuit Pulsed Current 1
I OA (SC) , I OB (SC) ,
100
mA
I OC (SC) , I OD (SC)
SWITCHING SPECIFICATIONS
Minimum Pulse Width 2
Maximum Switching Frequency 3
PW
5
100
ns
Mbps
C L = 200 pF, ED DISABLE = 0
C L = 200 pF, ED DISABLE = 0
Propagation Delay 4
t PHL , t PLH
99
110
128
ns
C L = 200 pF, ED DISABLE = 0
Change vs. Temperature
85
ps/°C
C L = 200 pF, ED DISABLE = 0
Pulse Width Distortion, |t PLH ? t PHL |
Channel-to-Channel Matching,
PWD
8
5
ns
ns
C L = 200 pF, ED DISABLE = 0
C L = 200 pF, ED DISABLE = 0
Rising vs. Rising Edges 5
Channel-to-Channel Matching,
9
ns
C L = 200 pF, ED DISABLE = 0
Falling vs. Falling Edges 5
Channel-to-Channel Matching,
13
ns
C L = 200 pF, ED DISABLE = 0
Rising vs. Falling Edges 6
Part-to-Part Matching, Rising or Falling Edges 7
10
ns
C L = 200 pF, ED DISABLE = 0,
input t R = 3 ns
Part-to-Part Matching, Rising vs. Falling Edges 8
18
ns
C L = 200 pF, ED DISABLE = 0,
input t R = 3 ns
Output Rise/Fall Time (10% to 90%)
t R /t F
25
ns
C L = 200 pF, ED DISABLE = 0
1
2
3
4
5
6
7
8
Short-circuit duration of less than 1 second. Average power must conform to the limit shown under the Absolute Maximum Ratings.
The minimum pulse width is the shortest pulse width at which the specified timing parameters are guaranteed.
The maximum switching frequency is the maximum signal frequency at which the specified timing parameters are guaranteed.
t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is
measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.
Channel-to-channel matching, rising, or falling edges is the magnitude of the propagation delay difference between any two channels of the same part when the
inputs are either both rising or falling edges. The supply voltages and the loads on each channel are equal.
Channel-to-channel matching, rising vs. falling edges is the magnitude of the propagation delay difference between any two channels of the same part when one
input is a rising edge and the other input is a falling edge. The supply voltages and loads on each channel are equal.
Part-to-part matching, rising, or falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when the inputs
are either both rising or falling edges. The supply voltages, temperatures, and loads of each part are equal.
Part-to-part matching, rising vs. falling edges is the magnitude of the propagation delay difference between the same channels of two different parts when one input
is a rising edge and the other input is a falling edge. The supply voltages, temperatures, and loads of each part are equal.
Rev. A | Page 3 of 12
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