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参数资料
| 型号： | ADUM1510BRWZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL ISOLATOR 16-SOIC |
| 标准包装： | 1,000 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 5/0 |
| 通道数： | 5 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 隔离： | 2500Vrms |
| 数据速率： | 10Mbps |
| 传输延迟： | 30ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 105°C |
Data Sheet
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1510 transformers. Figure 12 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen in Figure 12, the ADuM1510 is extremely
immune and is affected only by extremely large currents
operated at high frequency and very close to the component.
For example, at a magnetic field frequency of 1 MHz, a 0.5 kA
current would need to be placed 5 mm away from the
ADuM1510 to affect the operation of the component.
1000
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
ADuM1510
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
f r is the input stage refresh rate (Mbps).
To calculate the total I DD1 and I DD2 supply current, the supply
currents for each input and output channel corresponding to
I DD1 and I DD2 are calculated and totaled. Figure 4 and Figure 5
provide per-channel supply currents as a function of the data
rate for an unloaded output condition. Figure 6 provides per-
channel supply current as a function of the data rate for a 15 pF
output condition. Figure 7 and Figure 8 provide total I DD1 and
I DD2 supply current as a function of the data rate for ADuM1510
products.
POWER-UP/POWER-DOWN CONSIDERATIONS
Given that the ADuM1510 has separate supplies on each side of
the isolation barrier, the power-up and power-down charac-
teristics relative to each supply voltage need to be considered
individually.
As shown in Table 8, when V DD1 input power is off, the
ADuM1510 outputs take on a default low logic condition. As
the V DD1 supply is increased or decreased, the output of each
0.01
1k
10k
100k
1M
10M
100M
channel transitions from/to the default condition to/from the
state matching its respective signals (see Figure 13 and Figure 14).
MAGNETIC FIELD FREQUENCY (Hz)
Figure 12. Maximum Allowable Current for
Various Current-to-ADuM1510 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces can induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Care should be taken in the layout of such
traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM1510
isolator is a function of the supply voltage, the channel
data rate, and the channel output load.
OUTPUT
DATA
V DD1
2V
(TYP)
Figure 13. V DD1 Power-Up/Power-Down Characteristics, Input Data = High
For each input channel, the supply current is given by
I DDI = I DDI (Q)
I DDI = I DDI (D) × (2 f ? f r ) + I DDI (Q)
For each output channel, the supply current is given by
f ≤ 0.5 f r
f > 0.5 f r
V DD1
OUTPUT DATA
I DDO = I DDO (Q)
f ≤ 0.5 f r
Figure 14. V DD1 Power-Up/Power-Down Characteristics, Input Data = Low
I DDO = ( I DDO (D) + C L V DDO ) × (2 f ? f r ) + I DDO (Q) f ≤ 0.5 f r
where:
I DDI (Q) , I DDO (Q) are the specified input and output quiescent
supply currents (mA).
I DDI (D) , I DDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
C L is the output load capacitance (pF).
V DDO is the output supply voltage (V).
When V DD1 crosses the threshold for activating the refresh circuit
(approximately 2 V), there can be a delay of up to 2 μs before the
output is updated to the correct state, depending on the timing
of the next refresh pulse. When V DD1 is reduced from an on state
below the 2 V threshold, there can be a delay of up to 5 μs before
the output takes on its default low state. This corresponds to the
duration that the watchdog timer circuit at the input is designed
to wait before triggering an output default state.
Rev. B | Page 9 of 12
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