参数资料
型号: ADUM2250ARWZ-RL
厂商: Analog Devices Inc
文件页数: 10/16页
文件大小: 0K
描述: IC ISOLATOR I2C DUAL 5KV 16SOIC
标准包装: 1,000
系列: iCoupler®
输入 - 1 侧/2 侧: 2/2
通道数: 2
电源电压: 3 V ~ 5.5 V
电压 - 隔离: 5000Vrms
数据速率: 1Mbps
输出类型: I²C?
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
工作温度: -40°C ~ 105°C

The ADuM2250 / ADuM2251 interface on each side to I C sig-
ADuM2250/ADuM2251
APPLICATIONS INFORMATION
FUNCTIONAL DESCRIPTION
2
nals. Internally, the bidirectional I 2 C signals are split into two
unidirectional channels communicating in opposite directions
via dedicated i Coupler isolation channels. One channel of each
pair (the Side 1 input of each I/O pin in Figure 6) implements a
special input buffer and output driver that can differentiate between
externally generated inputs and its own output signals. It transfers
only externally generated input signals to the corresponding
Side 2 data or clock pin.
Both the Side 1 and Side 2 I 2 C pins are designed to interface to
an I 2 C bus operating in the 3.0 V to 5.5 V range. A logic low on
either side causes the corresponding I/O pin across the coupler
to be pulled low enough to comply with the logic low threshold
requirements of other I 2 C devices on the bus. Bus contention and
latch-up are avoided by guaranteeing that the input low threshold
at SDA 1 or SCL 1 is at least 50 mV less than the output low signal
Data Sheet
A bus segment is a portion of the I 2 C bus that is isolated from
other portions of the bus by galvanic isolation, bus extenders, or
level shifting buffers. Table 11 shows how multiple ADuM2250 /
ADuM2251 components can coexist on a bus as long as two
Side 1 buffers are not connected to the same bus segment.
Table 11. ADuM2250 / ADuM2251 Buffer Compatibility
Side 1 Side 2
Side 1 No Yes
Side 2 Yes Yes
The output logic low levels are independent of the V DD1 and
V DD2 voltages. The input logic low threshold at Side 1 is also
independent of V DD1 . However, the input logic low threshold at
Side 2 is designed to be at 0.3 V DD2 , consistent with I 2 C require-
ments. The Side 1 and Side 2 I/O pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
at the same pin. This prevents an output logic low at Side 1 from
being transmitted back to Side 2 and pulling down the I 2 C bus
GND 1
1
16
GND 2
by latching the state.
Because the Side 2 logic levels/thresholds and drive capabilities
comply fully with standard I 2 C values, multiple ADuM2250 /
NC
V DD1
2
3
ADuM2250
15
14
NC
V DD2
ADuM2251 devices connected to a bus by their Side 2 pins can
communicate with each other and with other I 2 C-compatible
devices, as shown in Figure 7. Note the distinction between I 2 C
compatibility and I 2 C compliance. I 2 C compatibility refers to situ-
ations in which the logic levels or drive capability of a component
do not necessarily meet the requirements of the I 2 C specification
but still allow the component to communicate with an I 2 C-com-
pliant device. I 2 C compliance refers to situations in which the
NC
SDA 1
SCL 1
GND 1
NC
4
5
6
7
8
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
13
12
11
10
9
NC
SDA 2
SCL 2
NC
GND 2
OPTIONAL
200?
ADuM2250
V DD1
V DD2
logic levels and drive capability of a component fully meet the
requirements of the I 2 C specification.
Because the Side 1 pin has a modified output level/input threshold,
Side 1 of the ADuM2250 / ADuM2251 can communicate only with
devices that are fully compliant with the I 2 C standard. In other
words, Side 2 of the ADuM2250 / ADuM2251 is I 2 C-compliant,
whereas Side 1 is only I 2 C-compatible.
The Side 1 I/O pins must not be connected to other I 2 C buffers
that implement a similar scheme of dual I/O threshold detection.
This latch-up prevention scheme is implemented in several popular
I 2 C level shifting and bus extension products currently available
from Analog Devices and other manufacturers. Care should be
SYMBOL INDICATES A DUAL THRESHOLD INPUT BUFFER.
NC = NO CONNECT
Figure 6. ADuM2250 Block Diagram
Figure 7 shows a typical application circuit, including the pull-up
resistors required for both Side 1 and Side 2 buses. Bypass capac-
itors with values from 0.01 μF to 0.1 μF are required between
V DD1 and GND 1 and between V DD2 and GND 2 . The 200 ? resistor
shown in Figure 7 is required for latch-up immunity if the ambient
temperature can be between 105°C and 125°C.
I 2 C BUS
1 16
2 15
MICRO-
3 14
PROCESSOR
taken to review the data sheet of potential I 2 C bus buffering prod-
ucts to ensure that only one buffer on a bus segment implements
a dual threshold scheme.
OR
SECONDARY
BUS
SEGMENT
SDA 1
SCL 1
GND 1
4
5
6
7
13
12
11
10
SDA 2
SCL 2
8
9
GND 2
Figure 7. Typical Isolated I 2 C Interface Using the ADuM2250
Rev. B | Page 10 of 16
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