参数资料
型号: ADUM3160BRWZ-RL
厂商: Analog Devices Inc
文件页数: 10/16页
文件大小: 0K
描述: IC ISOLATOR USB 2.5K 16SOIC
产品培训模块: iCoupler Digital Isolater Technology
标准包装: 1,000
系列: iCoupler®
输入 - 1 侧/2 侧: 2/2
通道数: 4
电源电压: 3 V ~ 5.5 V
电压 - 隔离: 2500Vrms
数据速率: 12Mbps
传输延迟: 70ns
输出类型: 逻辑
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 带卷 (TR)
工作温度: -40°C ~ 105°C
ADuM3160
COMPATIBILITY OF UPSTREAM APPLICATIONS
The ADuM3160 is designed specifically for isolating a USB
peripheral. However, the chip has two USB interfaces that meet
the electrical requirements for driving USB cables. This opens the
possibility of implementing isolation in downstream USB ports
such as isolated cables, which have generic connections to both
upstream and downstream devices, as well as isolating host ports.
In a fully compliant application, a downstream-facing port must
be able to detect whether a peripheral is low speed or full speed
based on the application of the upstream pull-up. The buffers
and logic conventions must adjust to match the requested speed.
Because the ADuM3160 sets its speed by hardwiring pins, the
part cannot adjust to different peripherals on the fly.
The practical result of using the ADuM3160 in a host port is
that the port works at a single speed. This behavior is acceptable
in embedded host applications; however, this type of interface is
not fully compliant as a general-purpose USB port.
Data Sheet
PRINTED CIRCUIT BOARD LAYOUT
The ADuM3160 digital isolator requires no external interface
circuitry for the logic interfaces. For full speed operation, the D+
and D? lines on each side of the device require a 24 Ω ± 1% series
termination resistor. These resistors are not required for low speed
applications. Power supply bypassing is required at the input and
output supply pins (see Figure 5). Install bypass capacitors between
V BUSx and V DDx on each side of the chip. The capacitors should have
a minimum value of 0.1 μF and low ESR. The total lead length
between both ends of the capacitor and the power supply pin
should not exceed 10 mm.
Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15
should also be considered unless the ground pair on each package
side is connected close to the package. All logic level signals are
3.3 V and should be referenced to the local V DDx pin or 3.3 V logic
signals from an external source.
V BUS1 = 5.0V INPUT V BUS2 = 3.3V INPUT
V DD1 = 3.3V OUTPUT V DD2 = 3.3V INPUT
Isolated cable applications have a similar issue. The cable operates
at the preset speed only; therefore, treat cable assemblies as custom
applications, not general-purpose isolated cables.
POWER SUPPLY OPTIONS
In most USB transceivers, 3.3 V is derived from the 5 V USB bus
V BUS1
GND 1
V DD1
PDEN
SPU
UD–
UD+
GND 1
ADuM3160
V BUS2
GND 2
V DD2
SPD
PIN
DD–
DD+
GND 2
through an LDO regulator. The ADuM3160 includes internal
LDO regulators on both the upstream and downstream sides. The
output of the LDO regulators is available on the V DD1 and V DD2 pins.
In some cases, especially on the peripheral side of the isolation,
there may not be a 5 V power supply available. The ADuM3160
has the ability to bypass the regulator and run on a 3.3 V supply
directly.
Two power pins are present on each side, V BUSx and V DDx . If 5 V
is supplied to V BUSx , an internal regulator creates 3.3 V to power
the xD+ and xD? drivers. V DDx provides external access to the
3.3 V supply to allow external bypass as well as bias for external
pull-ups. If only 3.3 V is available, it can be supplied to both V BUSx
and V DDx . This disables the regulator and powers the coupler
directly from the 3.3 V supply.
Figure 5 shows how to configure a typical application when the
upstream side of the coupler receives power directly from the USB
bus and the downstream side receives 3.3 V from the peripheral
power supply. The downstream side can run from a 5 V V BUS2
power supply as well. It can be connected in the same manner
as V BUS1 , as shown in Figure 5, if needed.
Figure 5. Suggested PCB Layout Example
In applications that involve high common-mode transients, care
should be taken to minimize board coupling across the isolation
barrier. Furthermore, design the board layout such that any coupling
that does occur affects all pins equally on a given component side.
Failure to ensure this can cause voltage differentials between pins
that exceed the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the transformer.
The decoder is bistable and is, therefore, either set or reset by the
pulses, indicating input logic transitions.
The limitation on the magnetic field immunity of the ADuM3160
is set by the condition in which induced voltage in the receiving
coil of the transformer is sufficiently large to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this may occur. The 3 V operating condition of the
ADuM3160 is examined because it represents the most suscep-
tible mode of operation.
Rev. C | Page 10 of 16
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