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| 型号： | ADUM4402CRWZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC DIGITAL ISOLATOR 4CH 16-SOIC |
| 标准包装： | 1,000 |
| 系列： | iCoupler® |
| 输入 - 1 侧/2 侧： | 2/2 |
| 通道数： | 4 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 电压 - 隔离： | 5000Vrms |
| 数据速率： | 90Mbps |
| 传输延迟： | 27ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 105°C |
Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM440x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 17). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V DD1 and between Pin 15 and
Pin 16 for V DD2 . The capacitor value should be between 0.01 μF
and 0.1 μF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair
ADuM4400/ADuM4401/ADuM4402
While the ADuM440x improve system-level ESD reliability,
they are no substitute for a robust system-level design. See the
AN-793 Application Note , ESD/Latch-Up Considerations with
iCoupler Isolation Products , for detailed recommendations on
board layout and system-level design.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the length of
time for a logic signal to propagate through a component. The
propagation delay to a logic low output can differ from the
propagation delay to logic high.
on each package side are connected close to the package.
INPUT (V Ix )
50%
V DD1
GND 1
V IA
V IB
V DD2
GND 2
V OA
V OB
OUTPUT (V Ox )
t PLH
t PHL
50%
V IC/ V OC
V ID/ V OD
NC/V E1
GND 1
V OC/ V IC
V OD/ V ID
V E2
GND 2
Figure 18. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
Figure 17. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
ensure that board coupling across the isolation barrier is
minimized. Furthermore, the board layout should be designed
such that any coupling that does occur equally affects all pins
on a given component side. Failure to ensure this could cause
voltage differentials between pins exceeding the Absolute
Maximum Ratings of the device, thereby leading to latch-up
or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
SYSTEM-LEVEL ESD CONSIDERATIONS AND
ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x) is
highly dependent on system design, which varies widely by
application. The ADuM440x incorporate many enhancements
to make ESD reliability less dependent on system design. The
enhancements include
? ESD protection cells added to all input/output interfaces.
? Key metal trace resistances reduced using wider geometry
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs among channels within a single
ADuM440x component.
Propagation delay skew refers to the maximum amount
the propagation delay differs among multiple ADuM440x
components operated under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the
decoder. The decoder is bistable and is therefore either set or
reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than approximately 5 μs,
the input side is assumed to be without power or nonfunctional;
in which case, the isolator output is forced to a default state (see
?
?
?
and paralleling of lines with vias.
The SCR effect, inherent in CMOS devices, minimized by
using guarding and isolation techniques between PMOS
and NMOS devices.
Areas of high electric field concentration eliminated using
45° corners on metal traces.
Supply pin overvoltage prevented with larger ESD clamps
between each supply pin and its respective ground.
Table 20) by the watchdog timer circuit.
The limitation on the ADuM440x magnetic field immunity
is set by the condition in which induced voltage in the trans-
former’s receiving coil is large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM440x is examined because it represents the most
susceptible mode of operation.
Rev. C | Page 15 of 20
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