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参数资料
| 型号： | ADUM6132ARWZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC GATE DRIVER ISOLATED 16-SOIC |
| 标准包装： | 1,000 |
| 系列： | isoPower® |
| 输入 - 1 侧/2 侧： | 2/0 |
| 通道数： | 2 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电压 - 隔离： | 3750Vrms |
| 传输延迟： | 60ns |
| 输出类型： | 逻辑 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 带卷 (TR) |
| 工作温度： | -40°C ~ 85°C |
ADuM6132
TERMINOLOGY
Channel-to-Channel Matching
Channel-to-channel matching with rising or falling matching
edge polarity is the magnitude of the propagation delay differ-
ence between two channels of the same part when the inputs
are both rising edges or both falling edges. The loads on each
channel are equal.
Channel-to-channel matching with rising vs. falling opposite
edge polarity is the magnitude of the propagation delay differ-
ence between two channels of the same part when one input is
a rising edge and one input is a falling edge. The loads on each
channel are equal.
Maximum Output Current
The maximum output current is the maximum isolated supply
current that the ADuM6132 can provide. This current supports
external loads as well as the needs of the ADuM6132 Channel A
output circuitry. This is achieved via external connection of the
V ISO pin to the V DDA pin and of the GND ISO pin to the GND A pin
(see Figure 16). The net current available to power external loads
is the ADuM6132 output current, I ISO , minus the Channel A
supply current, I DDA .
Maximum Switching Frequency
The maximum switching frequency is the maximum signal
frequency at which the specified timing parameters are guar-
anteed. Operation beyond the maximum switching frequency
is not recommended, because high switching rates can cause
droop in the output supply voltage.
Data Sheet
Minimum Pulse Width
The minimum pulse width is the shortest pulse width at which
the specified pulse width distortion is guaranteed. Operation
below the minimum pulse width is not recommended.
Part-to-Part Matching
Part-to-part matching is the magnitude of the propagation
delay difference between the same channels of two different
parts. This includes rising vs. rising edges, falling vs. falling
edges, or rising vs. falling edges. The supply voltages, temp-
eratures, and loads of each part are equal.
Propagation Delay
The propagation delay is the time that it takes a logic signal to
propagate through a component. The propagation delay to a
logic low output may differ from the propagation delay to a
logic high output.
The t PHL propagation delay is measured from the 50% level
of the falling edge of the V IA or V IB signal to the 50% level of
the falling edge of the V OA or V OB signal. The t PLH propagation
delay is measured from the 50% level of the rising edge of the
V IA or V IB signal to the 50% level of the rising edge of the V OA
or V OB signal.
Capacitive Load (C L )
The output capacitive load simulates a typical FET, IGBT, or
buffer for timing or current measurements. This load includes
all discrete and parasitic capacitive loads on the output.
Rev. B | Page 10 of 16
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