参数资料
| 型号： | ADV3228ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SW 16X8 72LFCSP |
| 标准包装： | 1 |
| 功能： | 交叉点开关 |
| 电路： | 1 x 8:8 |
| 电压电源： | 双电源 |
| 电压 - 电源，单路/双路(±)： | ±5V |
| 电流 - 电源： | 52mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 72-LFCSP-VQ（10x10） |
| 包装： | 托盘 |
ADV3228/ADV3229
Rev. 0 | Page 22 of 24
APPLICATIONS INFORMATION
The ADV3228/ADV3229 have two options for changing the
programming of the crosspoint matrix. In the first option, a
serial word of 40 bits can be provided, which updates the entire
matrix each time the 40-bit word is shifted into the device. The
second option allows for changing the programming of a single
output via a parallel interface. The serial option requires fewer
signals but more time (clock cycles) for changing the program-
ming, whereas the parallel programming technique requires
more signals but can change a single output at a time and requires
fewer clock cycles to complete the programming.
SERIAL PROGRAMMING
The serial programming mode uses the CE, CLK, DATAIN,
UPDATE, and SER/PAR pins. The first step is to assert a low
on SER/PAR to enable the serial programming mode. CE for
the chip must be low to allow data to be clocked into the device.
The CE signal can be used to address an individual device when
devices are connected in parallel.
The UPDATE signal should be high during the time that data is
shifted into the serial port of the device. Although the data still shifts
in when UPDATE is low, the transparent, asynchronous latches
allow the shifting data to reach the matrix, which causes the matrix
to try to update to every intermediate state as defined by the
shifting data.
The data at DATAIN is clocked in at every falling edge of CLK, and
a total of 40 bits must be shifted in to fill the register, and thereby,
complete the programming. For each of the eight outputs there are
five bits in the shift register; the position of these bits in the register
determines the output to which they apply (see Figure 6). Three of
the bits (D0 to D2) determine the source of the input that connects
to the output that pertains to the position in the register; the MSB is
shifted in first. The fourth bit (reserved) is a reserved enable bit and
must be shifted in as a logic high prior to D0 to D2 in all cases (in
parallel programming mode this bit is internally set high). The fifth
bit (D3) precedes these four bits and determines the enabled state
of the output. If D3 is low (output disabled), the four associated
bits do not matter because no input switches to that output.
The most significant output address data is shifted in first, and the
remaining addresses follow in sequence until the least significant
output address data is shifted in. At this point, UPDATE can be
taken low, which programs the device according to the data that
was just shifted in. The update registers are asynchronous, and
when UPDATE is low (and CE is low), they are transparent.
If more than one ADV3228/ADV3229 device is to be serially
programmed in a system, the DATAOUT signal from one device
can be connected to the DATAIN of the next device to form a serial
chain. Connect all of the CLK, CE, UPDATE, and SER/PAR pins in
parallel and operate them as described previously in this section.
The serial data is input to the DATAIN pin of the first device of
the chain, and it ripples through to the last. Therefore, the data for
the last device in the chain should come at the beginning of the
programming sequence. The length of the programming sequence
(40 bits) is multiplied by the number of devices in the chain.
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
Parallel programming allows the modification of a single output
at a time. Because this takes only one CLK/UPDATE cycle, signifi-
cant time savings can be realized by using parallel programming.
An important consideration in using parallel programming is
that the RESET signal does not reset all registers in the ADV3228/
ADV3229. When taken low, the RESET signal sets each output
to the disabled state. This is helpful during power-up to ensure
that two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
contain random data, even though the RESET signal was asserted.
If parallel programming is used to program one output, that
output is properly programmed, but the rest of the device has a
random program state depending on the internal register content
at power-up. Therefore, when using parallel programming, it is
essential that all outputs be programmed to a desired state after
power-up to ensure that the programming matrix is always in a
known state. From this point, parallel programming can be used
to modify either a single output or multiple outputs at one time.
Similarly, if both CE and UPDATE are taken low after initial
power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent programming
the crosspoint into an unknown state, do not apply low logic levels
to both CE and UPDATE after power is initially applied. To eliminate
the possibility of programming the matrix to an unknown state,
after initial power-up, program the full shift register one time to
a desired state using either serial or parallel programming.
To change the programming of an output via parallel programming,
take the SER/PAR and UPDATE pins high, and take the CE pin
low. The CLK signal should be in the high state. Place the 3-bit
address of the output to be programmed on A0 to A2. The first
three data bits (D0 to D2) contain the information that identifies
the input that is programmed to the addressed output. A fourth bit,
reserved, is a reserved enable bit and is internally connected to a
logic high level in parallel programming mode. The fifth data bit
(D3) determines the enabled state of the output. If D3 is low
(output disabled), the data bits on D0 to D2 do not matter.
After the address and data signals are established, they can be
latched into the shift register by pulling the CLK signal low;
however, the matrix is not programmed until the UPDATE signal
is taken low. In this way, it is possible to latch in new data for
several or all of the outputs first via successive negative transitions
of CLK while UPDATE is held high and then have all the new data
take effect when UPDATE goes low. Use this technique when
programming the device for the first time after power-up when
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相关代理商/技术参数 |
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| ADV3229ACPZ | 功能描述:IC CROSSPOINT SW 16X8 72LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 功能:开关 电路:单刀单掷 导通状态电阻:48 欧姆 电压电源:单电源 电压 - 电源，单路/双路(±):2.7 V ~ 5.5 V 电流 - 电源:5µA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:托盘 |
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