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| 型号： | ADV7125JSTZ330 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/16页 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO 3CH 330MHZ 48LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 位数： | 8 |
| 转换器数目： | 3 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 30mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 6 电流，单极 |
| 采样率（每秒）： | 330M |
ADV7125
Rev. C | Page 6 of 16
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 4.
Parameter3
Symbol
Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay,
t6
7.5
ns
Analog Output Rise/Fall Time4
t7
1.0
ns
Analog Output Transition Time5
t8
15
ns
Analog Output Skew6
t9
1
2
ns
CLOCK CONTROL
CLOCK Frequency7
fCLK
50
MHz
50 MHz grade
140
MHz
140 MHz grade
240
MHz
240 MHz grade
330
MHz
330 MHz grade
t1
0.2
ns
t2
1.5
ns
CLOCK Period
t3
3
ns
t4
1.4
ns
fCLK_MAX = 330 MHz
t5
1.4
ns
fCLK_MAX = 330 MHz
t4
1.875
ns
fCLK_MAX = 240 MHz
t5
1.875
ns
fCLK_MAX = 240 MHz
t4
2.85
ns
fCLK_MAX = 140 MHz
t5
2.85
ns
fCLK_MAX = 140 MHz
CLOCK Pulse Width High
t4
8.0
ns
fCLK_MAX = 50 MHz
CLOCK Pulse Width Low
t5
8.0
ns
fCLK_MAX = 50 MHz
tPD
1.0
Clock cycles
PSAVE Up Time6
t10
4
10
ns
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: 40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
t3
t1
t4
t8
t2
t6
t7
t5
CLOCK
DIGITAL INPUTS
(R7 TO R0, G7 TO G0, B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
NOTES
1. OUTPUT DELAY (
t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
03
09
7-
0
02
Figure 2. Timing Diagram
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