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| 型号： | ADV7171KSUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/64页 |
| 文件大小： | 0K |
| 描述： | IC DAC VIDEO ENC NTSC 44TQFP |
| 产品培训模块： | Interfacing AV Converters to Blackfin Processors |
| 标准包装： | 1 |
| 类型： | 视频编码器 |
| 应用： | 机顶盒，视频播放器 |
| 电压 - 电源，模拟： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 786 (CN2011-ZH PDF) |
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ADV7170/ADV7171
Rev. C | Page 33 of 64
MR41
MR40
MR47
MR42
MR44
MR43
MR45
MR46
OUTPUT SELECT
0
YC OUTPUT
1
RGB/YUV OUTPUT
MR40
RGB SYNC
0
DISABLE
1
ENABLE
MR42
PEDESTAL
CONTROL
0
PEDESTAL OFF
1
PEDESTAL ON
MR44
SLEEP MODE
CONTROL
0
DISABLE
1
ENABLE
MR46
ACTIVE VIDEO
FILTER CONTROL
0
DISABLE
1
ENABLE
MR45
MR47
(0)
ZERO SHOULD
BE WRITTEN TO
THIS BIT
VSYNC_3H
0
DISABLE
1
ENABLE
MR43
RGB/YUV
CONTROL
0
RGB OUTPUT
1
YUV OUTPUT
MR41
00221-042
Figure 42. Mode Register 4
MODE REGISTER 4 MR4 (MR47 TO MR40)
(Address (SR4 to SR0) = 04H)
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the
various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)
This bit specifies if the part is in composite video mode or
RGB/YUV mode. Note that in RGB/YUV mode the composite
signal is still available.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync
information encoded on all RGB outputs.
VSYNC_3H (MR43)
When this bit is enabled (1) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode and
3 lines in NTSC mode. When this bit is enabled in master
mode, the ADV7170/ADV7171 output an active low VSYNC
signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.
Pedestal Control (MR44)
This bit specifies whether a pedestal is to be generated on the
NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 are configured in PAL mode.
Active Video Filter Control (MR45)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the sync rise and fall
times are always on spec regardless of which luma filter is
selected. This mode is enabled by a Logic Level 1.
Sleep Mode Control (MR46)
When this bit is set to 1, sleep mode is enabled. With this mode
enabled, power consumption of the ADV7170/ADV7171 is
reduced to typically 200 nA. The I2C registers can be written to
and read from when the ADV7170/ADV7171 are in sleep
mode. If MR46 is set to a 0 when the device is in sleep mode,
the ADV7170/ADV7171 come out of sleep mode and resume
normal operation. Also, if the RESET signal is applied during
sleep mode, the ADV7170/ADV7171 come out of sleep mode
and resume normal operation.
Reserved (MR47)
A Logic Level 0 should be written to this bit.
TIMING MODE REGISTER 0 (TR07 TO TR00)
(Address [SR4 to SR0] = 07H)
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7171KSUZ-REEL | 功能描述:IC DAC VIDEO ENC NTSC 44TQFP TR RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7171KSZ | 功能描述:IC DAC VIDEO ENC NTSC 44-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7171KSZ | 制造商:Analog Devices 功能描述:IC, VIDEO ENCODER, 10BIT, MQFP-44 |
| ADV7171KSZ-REEL | 功能描述:IC DAC VIDEO ENC NTSC 44-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7171SU | 制造商:AD 制造商全称:Analog Devices 功能描述:Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
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