参数资料
型号: ADV7179KCPZ
厂商: Analog Devices Inc
文件页数: 16/52页
文件大小: 0K
描述: IC ENCODER VID NTSC/PAL 40LFCSP
产品培训模块: Interfacing AV Converters to Blackfin Processors
标准包装: 1
类型: 视频编码器
应用: 数码相机,手机,便携式视频
电压 - 电源,模拟: 2.8 V,3.3 V
安装类型: 表面贴装
封装/外壳: 40-VFQFN 裸露焊盘,CSP
供应商设备封装: 40-LFCSP-VQ(6x6)
包装: 托盘
产品目录页面: 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 23 of 52
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A
VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in
(NTSC) and
(PAL).
illustrates the
HSYNC, BLANK, and VSYNC for an even-to-
odd field transition relative to the pixel data.
illustrates the
HSYNC, BLANK, and VSYNC for an odd-to-
even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
02980-A
-029
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
VSYNC
PIXEL
DATA
Cb
Y
Cr
Y
Cb
HSYNC
BLANK
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
PAL = 864
× CLOCK/2
NTSC = 858
× CLOCK/2
02980-A
-082
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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