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参数资料
型号： ADV7180KCP32Z
厂商： Analog Devices Inc
文件页数： 8/116页
文件大小： 0K
描述： IC VIDEO DECODER 10BIT 32LFCSP
设计资源： Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060)
Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
标准包装： 1
类型： 视频解码器
应用： 数码相机，手机，便携式视频
安装类型： 表面贴装
封装/外壳： 32-WFQFN 裸露焊盘，CSP
供应商设备封装： 32-LFCSP-WQ（5x5）
包装： 托盘
Data Sheet
ADV7180
Rev. I | Page 105 of 116
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x74
VDP_LINE_01E
VBI_DATA_P334_N282[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 334 (PAL), Line 282 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P21_N19[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 21 (PAL), Line 19 (NTSC)
0x75
VDP_LINE_01F
VBI_DATA_P335_N283[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 335 (PAL), Line 283 (NTSC)
MAN_LINE_PGM must be
set to 1 for these bits to
be effective
VBI_DATA_P22_N20[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 22 (PAL), Line 20 (NTSC)
0x76
VDP_LINE_020
VBI_DATA_P336_N284[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 336 (PAL), Line 284 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P23_N21[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 23 (PAL), Line 21 (NTSC)
0x77
VDP_LINE_021
VBI_DATA_P337_N285[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 337 (PAL), Line 285 (NTSC)
MAN_LINE_PGM must
be set to 1 for these bits
to be effective
VBI_DATA_P24_N22[3:0]
0 0 0 0
Sets VBI standard to be decoded from
Line 24 (PAL), Line 22 (NTSC)
0x78
VDP_STATUS
(read only)
CC_AVL
0
Closed captioning not detected
CC_CLEAR resets the
CC_AVL bit
1
Closed captioning detected
CC_EVEN_FIELD
0
Closed captioning decoded from
odd field
1
Closed captioning decoded from
even field
CGMS_WSS_AVL
0
CGMS/WSS not detected
CGMS_WSS_CLEAR resets
the CGMS_WSS_AVL bit
1
CGMS/WSS detected
Reserved
0
GS_PDC_VPS_UTC_AVL
0
GS/PDC/VPS/UTC not detected
GS_PDC_VPS_UTC_CLEAR
resets the
GS_PDC_VPS_UTC_AVL
bit
1
GS/PDC/VPS/UTC detected
GS_DATA_TYPE
0
Gemstar_1× detected
1
Gemstar_2× detected
VITC_AVL
0
VITC not detected
VITC_CLEAR resets the
VITC_AVL bit
1
VITC detected
TTXT_AVL
0
Teletext not detected
1
Teletext detected
VDP_STATUS_CLEAR
(write only)
CC_CLEAR
0
Does not reinitialize the CCAP readback
registers
This is a self-clearing bit
1
Reinitializes the CCAP readback registers
Reserved
0
CGMS_WSS_CLEAR
0
Does not reinitialize the CGMS/WSS
readback registers
This is a self-clearing bit
1
Reinitializes the CGMS/WSS readback
registers
Reserved
0
GS_PDC_VPS_UTC_CLEAR
0
Does not reinitialize the GS/PDC/VPS/
UTC readback registers
This is a self-clearing bit
1
Refreshes the GS/PDC/VPS/UTC
readback registers
Reserved
0
VITC_CLEAR
0
Does not reinitialize the VITC readback
registers
This is a self-clearing bit
1
Reinitializes the VITC readback registers
Reserved
0
0x79
VDP_CCAP_DATA_0
(read only)
CCAP_BYTE_1[7:0]
x x x x x x x x
Decoded Byte 1 of CCAP
0x7A
VDP_CCAP_DATA_1
(read only)
CCAP_BYTE_2[7:0]
x x x x x x x x
Decoded Byte 2 of CCAP
0x7D
VDP_CGMS_WSS_DATA_0
(read only)
CGMS_CRC[5:2]
x x x x
Decoded CRC sequence for CGMS
Reserved
0 0 0 0
0x7E
VDP_CGMS_WSS_DATA_1
(read only)
CGMS_WSS[13:8]
x x x x x x
Decoded CGMS/WSS data
CGMS_CRC[1:0]
x x
Decoded CRC sequence for CGMS
0x7F
VDP_CGMS_WSS_DATA_2
(read only)
CGMS_WSS[7:0]
x x x x x x x x
Decoded CGMS/WSS data
0x84
VDP_GS_VPS_PDC_UTC_0
(read only)
GS_VPS_PDC_UTC_BYTE_0[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
0x85
VDP_GS_VPS_PDC_UTC_1
(read only)
GS_VPS_PDC_UTC_BYTE_1[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
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