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参数资料
| 型号： | ADV7181DBCPZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO DECODER SD/HD 64LFCSP |
| 标准包装： | 2,500 |
| 系列： | * |
Data Sheet
ADV7181D
Rev. A | Page 11 of 24
Pin No.
Mnemonic
Type
Description
34 to 38, 45 to 49
A
IN1 to AIN10
Input
Analog Video Input Channels.
39, 40
CAPY1, CAPY2
Input
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for
these pins.
41
AVDD
Power
Analog Supply Voltage (3.3 V).
42
REFOUT
Output
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor network
for this pin.
43
CML
Output
Common-Mode Level Pin for the Internal ADCs. See Figure 9 for a recommended
capacitor network for this pin.
44
CAPC2
Input
ADC Capacitor Network. See Figure 9 for a recommended capacitor network for this pin.
50
SOY
Input
Sync on Luma Input. Used in embedded synchronization mode.
51
RESET
Input
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7181D circuitry.
52
ALSB
Input
set to Logic 0, this pin sets the address for a write to Control Port 0x40 and the readback
address for VBI Port 0x21. When set to Logic 1, this pin sets the address for a write to
Control Port 0x42 and the readback address for VBI Port 0x23.
53
SDATA
Input/
Output
I2C Port Serial Data Input/Output Pin.
54
SCLK
Input
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
55
VS_IN
Input
Vertical Synchronization Input Signal. This pin can be configured in CP mode to extract
timing in a 5-wire mode.
56
HS_IN/CS_IN
Input
Horizontal Synchronization Input Signal (HS_IN). This pin can be configured in CP mode
to extract timing in a 5-wire mode.
Composite Synchronization Input Signal (CS_IN). This pin can be configured in CP mode
to extract timing in a 4-wire mode.
63
FIELD/DE
Output
Field Synchronization Output Signal (FIELD). Used in all interlaced video modes.
Data Enable Signal (DE). This pin can also be used as a data enable (DE) signal in CP mode
to allow direct connection to an HDMI/DVI transmitter IC.
64
VS
Output
Vertical Synchronization Output Signal (SDP and CP Modes).
EP
Exposed Pad
The exposed pad must be connected to GND.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7181DWBCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 10-Channel, Multiformat SDTV/HDTV |
| ADV7181DWBCPZ-RL | 功能描述:IC VIDEO DECODER SD/HD 64LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:* 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7181KCP | 制造商:Analog Devices 功能描述:9-BIT BIT NTSC/PAL/SECAM VIDEO DECODER - Bulk |
| ADV7181KST | 制造商:Analog Devices 功能描述:9-BIT BIT NTSC/PAL/SECAM VIDEO DECODER - Bulk |
| ADV7181WBCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer |
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