参数资料
| 型号： | ADV7533BCBZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/12页 |
| 文件大小： | 0K |
| 描述： | IC TX RX HDMI/DVI 49WLSCP |
| 标准包装： | 5,000 |
| 类型： | HDMI，DVI 发射器 |
| 应用： | 数码相机，手机，便携式视频 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 49-WFBGA，WLCSP |
| 供应商设备封装： | 49-WLCSP（3.46x3.46） |
| 包装： | 带卷 (TR) |
Data Sheet
ADV7533
Rev. A | Page 9 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7533
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09
82
1-
0
03
1
A
B
C
D
E
F
G
234
BALL A1
CORNER
56
7
DRxC–
DRx0–
DRx1–
DRx2–
DRx3–
DRxC+
DRx0+
DRx1+
DRx2+
DRx3+
V1P2
GND
V3P3
GND
DVDD
SCL
DDCSCL
DDCSDA
SCLK/MCLK
SDA
V1P2
LRCLK
GND
CECCLK
A2VDD
CEC
SPDIF/I2S
AVDD
DVDD
PVDD
PD
HPD
REXT
INT
Tx2+
TxC–
TxC+
Tx0–
Tx0+
Tx1–
Tx1+
Tx2–
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
F6, G6
DRx3/DRx3+
I
MIPI/DSI Differential Pair for Lane 3. Unused channel should be connected to ground.
F5, G5
DRx2/DRx2+
I
MIPI/DSI Differential Pair for Lane 2. Unused channel should be connected to ground.
F4, G4
DRx1/DRx1+
I
MIPI/DSI Differential Pair for Lane 1.
F3, G3
DRx0/DRx0+
I
MIPI/DSI Differential Pair for Lane 0.
F2, G2
DRxC/DRxC+
I
MIPI/DSI Differential Clock.
C3
PD
I
Power-Down. Programmable polarity is determined at power-up. The I2C address and
the PD polarity are set by the PD pin state when the supplies are applied to the
ADV7533. Internally pulled up for 1; if 0 desired, pull down to ground with a 2 kΩ
resistor. Supports typical CMOS logic levels from 1.8 V up to 3.3 V.
C5
R_EXT
I
Sets internal reference currents. Place a 1 KΩ resistor (1% tolerance) between this pin
and ground.
C4
HPD
I
Hot Plug Detect Signal. Indicates to the interface whether the receiver is connected. 1.8
V to 5.0 V CMOS logic level.
C1
SPDIF/I2S
I
S/PDIF or I2S Audio Data Input. Represents the S/PDIF block or the two channels of
audio available through I2S. Supports typical CMOS logic levels from1.8 V to 3.3 V.
C2
SCLK/MCLK
I
Audio Clock. Supports typical CMOS logic levels from1.8 V to 3.3 V. Unused input should
be connected to ground.
D3
LRCLK
I
Audio Left/Right Clock Input. Supports typical CMOS logic levels from1.8 V to 3.3 V.
Unused input should be connected to ground.
B7, A7
TxC/TxC+
O
Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level.
A2, A1
Tx2/Tx2+
O
Differential Output Channel 2. Differential output of the red data at 10× the pixel clock
rate; TMDS logic level.
A4, A3
Tx1/Tx1+
O
Differential Output Channel 1. Differential output of the green data at 10× the pixel
clock rate; TMDS logic level.
A6, A5
Tx0/Tx0+
O
Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock
rate; TMDS logic level.
D5
INT
O
Interrupt. CMOS logic level. A 2 kΩ pull-up resistor to interrupt the microcontroller I/O
supply is recommended. This is a low active signal.
B4
AVDD
P
1.8 V Power Supply for TMDS Outputs. Should be filtered and as quiet as possible.
D4, E3
V1P2
P
Digital Logic Supply (1.2 V or 1.8 V). Set to 1.2 V for lowest power consumption. Should
be filtered and as quiet as possible.
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