
ADV7850
Data Sheet
Rev. 0 | Page 22 of 32
Pin No.
Mnemonic
Description
AA14
DQ11
SDRAM Data Line.
AA15
UDQSN
SDRAM Upper Data Strobe Complement Signal.
AA16
SDVDD
Memory Interface Supply.
AA17
GND
Ground.
AA18
HS_IN1/TRI7
HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The
HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the
SCART or D-connector.
AA19
VS_IN1/TRI8
VS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS
input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or
D-connector.
AA20
GND
Ground.
AA21
TRI3
Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector.
AA22
HS_IN2/TRI5
HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The
HS input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the
SCART or D-connector.
AA23
VS_IN2/TRI6
HS on Graphics Port/Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector. The VS
input signal is used for 5-wire timing mode. This ball can also be used as a trilevel/bilevel input on the SCART or
D-connector.
AB1
GND
Ground.
AB2
TX_PVDD
HDMI Tx Digital Supply (1.8 V).
AB3
TX_PLVDD
HDMI Tx PLL Digital Supply (1.8 V). It is important to ensure that this supply pin has a clean voltage input.
AB4
SDVDD
Memory Interface Supply.
AB5
A11
SDRAM Address Line.
AB6
A6
SDRAM Address Line.
AB7
A2
SDRAM Address Line.
AB8
CAS
SDRAM Interface Column Address Select Command Signal. One of four command signals to the external
SDRAM.
AB9
RAS
SDRAM Interface Row Address Select Command Signal. One of four command signals to the external SDRAM.
AB10
VREF
Termination Reference Voltage for Memory Interface.
AB11
SDVDD
Memory Interface Supply.
AB12
LDQSN
SDRAM Lower Data Strobe Complement Signal.
AB13
DQ3
SDRAM Data Line.
AB14
DQ10
SDRAM Data Line.
AB15
DQ12
SDRAM Data Line.
AB16
DQ14
SDRAM Data Line.
AB17
GND
Ground.
AB18
SYNC1
This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.
AB19
AVIN3
Analog Video Mux Input Channel.
AB20
GND
Ground.
AB21
SYNC2
This is a synchronization on green or luma input (SOG/SOY) used in embedded synchronization mode.
AB22
AVIN6
Analog Video Mux Input Channel.
AB23
TRI4
Digital Input Capable of Slicing Bilevel or Trilevel Input from SCART or D-Connector.
AC1
GND
Ground.
AC2
TX_RTERM
This signal sets the internal termination resistance. A 500 Ωresistor between this ball and GND should be used.
AC3
TX_VDD33
HDMI Tx PLL Regulator Supply Input (3.3V). This pin is an internal voltage regulator input.
AC4
SDVDD
Memory Interface Supply.
AC5
A8
SDRAM Address Line.
AC6
A4
SDRAM Address Line.
AC7
A0
SDRAM Address Line.
AC8
CS
SDRAM Interface Chip Select. SDRAM CS enables and disables the command decoder on the RAM. One of four
command signals to the external SDRAM.
AC9
CKN
SDRAM Interface Differential Clock Compliment Output. All address and control output signals to the RAM
should be sampled on the positive edge of CK and on the negative edge of CKN.
AC10
CK
SDRAM Interface Differential Clock Right Output. All address and control output signals to the RAM should be
sampled on the positive edge of CK and on the negative edge of CKN.