参数资料
型号: ADZS-BF609-EZBRD
厂商: Analog Devices Inc
文件页数: 33/98页
文件大小: 0K
描述: KIT EVAL EZ-BOARD ADSP-BF60X
标准包装: 1
系列: Blackfin®
类型: DSP
适用于相关产品: ADSP-BF60x
所含物品: 板,线缆,电源
Using ADSP-BF609 EZ-KIT Lite
SPI Interface
THE ADSP-BF609 PROCESSOR HAS TWO SPI INTERFACES, SPI0 AND SPI1 . SPI0 IS
CONNECTED TO A WINBOND W25Q32BV 32 MB SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI SUPPORT.
QUAD MODE IS ENABLED BY DEFAULT. THE PROCESSOR FLAG SIGNALS, PD00 AND
PD01 ( SPI0 D2
AND D3 ), CAN BE DISCONNECTED BY USING SOFTCONFIG. REFER TO
“SOFTWARE-CONTROLLED SWITCHES (SOFTCONFIG)” ON PAGE 2-3 FOR MORE INFOR-
MATION. BY DEFAULT, THE SPI0 CHIP SELECT 1 IS CONNECTED TO THE MEMORY
DEVICE. THIS CAN ALSO BE DISCONNECTED BY USING SOFTCONFIG.
SMC Interface
THE STATIC MEMORY CONTROLLER (SMC) INTERFACE OF THE ADSP-BF609
EZ-KIT LITE CONTAINS A 32 MB (16M X 16) NUMONYX PC28F128P33B
PARALLEL FLASH CHIP. FLASH MEMORY IS CONNECTED TO THE 16-BIT DATA BUS AND
ADDRESS LINES 1 – 23. CHIP ENABLE IS DECODED BY USING SMC0_AMS0 .
THE FLASH MEMORY IS BOTTOM BOOT AND PROVIDES ONE-TIME-PROGRAMMABLE
(OTP) MEMORY.
FLASH MEMORY IS PRE-LOADED WITH BOOT CODE FOR THE POST PROGRAM. FOR
MORE INFORMATION, REFER TO “POWER-ON-SELF TEST” ON PAGE 1-20 .
Ethernet Interface
THE ADSP-BF609 PROCESSOR HAS TWO REDUCED MEDIA INDEPENDENT INTER-
FACES (RMIIS), ONE OF WHICH CONNECTS TO AN EXTERNAL ETHERNET PHY DEVICE.
THE EZ-KIT LITE PROVIDES A NATIONAL DP83848C, AUTO-MDIX, FULLY
COMPLIANT PHY WITH IEEE 802.2/802.2U STANDARDS. THE PHY SUPPORTS
10BASE-T AND 100BASE-TX OPERATIONS. THE PHY AND PROCESSOR SUPPORT
IEEE 1588 TIME STAMPING, AVAILABLE ON THE EZ-KIT LITE VIA A STANDARD
ADSP-BF609 EZ-KIT LITE EVALUATION SYSTEM MANUAL
1-13
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