Fusion Family of Mixed Signal FPGAs
Revision 4
2-133
Table 2-57 details the settings available to control the prescaler values of the AV, AC, and AT pins. Note
that the AT pin has a reduced number of available prescaler values.
Table 2-58 details the settings available to control the MUX within each of the AV, AC, and AT circuits.
This MUX determines whether the signal routed to the ADC is the direct analog input, prescaled signal,
or output of either the Current Monitor Block or the Temperature Monitor Block.
Table 2-59 details the settings available to control the Direct Analog Input switch for the AV, AC, and AT
pins.
Table 2-60 details the settings available to control the polarity of the signals coming to the AV, AC, and AT
pins. Note that the only valid setting for the AT pin is logic 0 to support positive voltages.
Table 2-57 Prescaler Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)
Control Lines
Bx[2:0]
Scaling
Factor, Pad to
ADC Input
LSB for an
8-Bit
Conversion1
(mV)
LSB for a
10-Bit
Conversion1
(mV)
LSB for a
12-Bit
Conversion1
(mV)
Full-Scale
Voltage in
10-Bit
Mode2
Range Name
000 3
0.15625
64
16
4
16.368 V
16 V
001
0.3125
32
8
2
8.184 V
8 V
010 3
0.625
16
4
1
4.092 V
4 V
011
1.25
8
2
0.5
2.046 V
2 V
100
2.5
4
1
0.25
1.023 V
1 V
101
5.0
2
0.5
0.125
0.5115 V
0.5 V
110
10.0
1
0.25
0.0625
0.25575 V
0.25 V
111
20.0
0.5
0.125
0.03125
0.127875 V
0.125 V
Notes:
1. LSB voltage equivalences assume VAREF = 2.56 V.
2. Full Scale voltage for n-bit mode: ((2^n) - 1) x (LSB for a n-bit Conversion)
3. These are the only valid ranges for the Temperature Monitor Block Prescaler.
Table 2-58 Analog Multiplexer Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)
Control Lines Bx[4]
Control Lines Bx[3]
ADC Connected To
0
Prescaler
0
1
Direct input
1
0
Current amplifier temperature monitor
1
Not valid
Table 2-59 Direct Analog Input Switch Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)
Control Lines Bx[5]
Direct Input Switch
0
Off
1
On
Table 2-60 Voltage Polarity Control Truth Table—AV (x = 0), AC (x = 1), and AT (x = 3)*
Control Lines Bx[6]
Input Signal Polarity
0
Positive
1
Negative
Note: *The B3[6] signal for the AT pad should be kept at logic 0 to accept only positive voltages.