IGLOO DC and Switching Characteristics
2-4
Revision 23
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the
output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the ProASIC3 and ProASIC3E FPGA fabric user’s guides for information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
Figure 2-1 V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
V
a = 0.85 V ± 0.25 V
Deactivation trip point:
V
d = 0.75 V ± 0.25 V
Activation trip point:
V
a = 0.9 V ± 0.3 V
Deactivation trip point:
V
d = 0.8 V ± 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCI + VT