参数资料
型号: AGLE600V2-FGG484C
元件分类: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封装: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-256
文件页数: 74/156页
文件大小: 5023K
代理商: AGLE600V2-FGG484C
IGLOOe DC and Switching Characteristics
2- 10
Advance v0.3
Table 2-13 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD
(pF)
VCCI
(V)
Static Power
PDC7 (mW)
2
Dynamic Power
PAC10 (W/MHz)
3
Single-Ended
3.3 V LVTTL/LVCMOS
5
3.3
148.00
2.5 V LVCMOS
5
2.5
83.23
1.8 V LVCMOS
5
1.8
54.58
1.5 V LVCMOS (JESD8-11)
5
1.5
37.05
1.2 V LVCMOS 4
5
1.2
17.94
3.3 V PCI
10
3.3
204.61
3.3 V PCI-X
10
3.3
204.61
Voltage-Referenced
3.3 V GTL
10
3.3
24.08
2.5 V GTL
10
2.5
13.52
3.3 V GTL+
10
3.3
24.10
2.5 V GTL+
10
2.5
13.54
HSTL (I)
20
1.5
7.08
26.22
HSTL (II)
20
1.5
13.88
27.22
SSTL2 (I)
30
2.5
16.69
105.56
SSTL2 (II)
30
2.5
25.91
116.60
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS
2.5
7.70
89.62
LVPECL
3.3
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output
slew.
2. PDC7 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCCI.
4. Applicable for IGLOOe V2 devices only.
相关PDF资料
PDF描述
AGLE600V5-FFG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V5-FFGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
AGLE600V5-FG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
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