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参数资料
型号： AGLE600V5-FG484C
元件分类： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA484
封装： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, FBGA-484
文件页数： 94/156页
文件大小： 5023K
代理商： AGLE600V5-FG484C
IGLOOe DC and Switching Characteristics
2- 28
Advance v0.3
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 110°C, the short current condition would have to be sustained for more than three
months to cause a reliability concern. The I/O design does not contain any short circuit protection,
but such protection would only be needed in extremely prolonged stress conditions.
Table 2-30 Duration of Short Circuit Event before Failure
Temperature
Time before Failure
–40°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
110°C
3 months
Table 2-31 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV
Table 2-32 I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer
Input Rise/Fall Time (min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns*
20 years (110°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but input noise
voltage
cannot
exceed
Schmitt
hysteresis.
20 years (110°C)
HSTL/SSTL/GTL
No requirement
10 ns*
10 years (100°C)
LVDS/B-LVDS/M-LVDS/LVPECL
No requirement
10 ns*
10 years (100°C)
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,
then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity
evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
相关PDF资料
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AGLE600V5-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
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