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参数资料
型号： AGLN010V2-UCG36I
厂商： Microsemi SoC
文件页数： 51/150页
文件大小： 0K
描述： IC FPGA NANO 1KB 10K 36-UCSP
标准包装： 714
系列： IGLOO nano
逻辑元件/单元数： 260
输入/输出数： 23
门数： 10000
电源电压： 1.14 V ~ 1.575 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 36-WFBGA，CSBGA
供应商设备封装： 36-UCSP（3x3）
Datasheet Information
5-4
Revision 17
Revision 10
(continued)
The following tables were updated with current available information. The equivalent
software default drive strength option was added.
Table 2-21 Summary of Maximum and Minimum DC Input and Output Levels
Table 2-25 Summary of I/O Timing Characteristics—Software Default Settings
Table 2-26 Summary of I/O Timing Characteristics—Software Default Settings
Table 2-28 I/O Output Buffer Maximum Resistances 1
Table 2-29 I/O Weak Pull-Up/Pull-Down Resistances
Table 2-30 I/O Short Currents IOSH/IOSL
Timing tables in the "Single-Ended I/O Characteristics" section, including new tables for
3.3 V and 1.2 V LVCMOS wide range.
Table 2-40 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V
Wide Range
Table 2-63 Minimum and Maximum DC Input and Output Levels
Table 2-67 Minimum and Maximum DC Input and Output Levels (new)
2-19
through
2-40
The formulas in the notes to Table 2-29 I/O Weak Pull-Up/Pull-Down Resistances were
revised (SAR 21348).
2-24
The text introducing Table 2-31 Duration of Short Circuit Event before Failure was
revised to state six months at 100° instead of three months at 110° for reliability
concerns. The row for 110° was removed from the table.
2-25
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): "It
uses a 5-V tolerant input buffer and push-pull output buffer."
2-32
The FDDRIMAX and FDDOMAX values were added to tables in the "DDR Module
Specifications" section (SAR 23919). A note was added stating that DDR is not
supported for AGLN010, AGLN015, and AGLN020.
2-51
Tables in the "Global Tree Timing Characteristics" section were updated with new
information available.
2-64
Table 2-100 IGLOO nano CCC/PLL Specification and Table 2-101 IGLOO nano
CCC/PLL Specification were revised (SAR 79390).
2-70,
2-71
Tables in the SRAM "Timing Characteristics" section and FIFO "Timing Characteristics"
section were updated with new information available.
2-77,
2-85
Table 3-3 TRST and TCK Pull-Down Recommendations is new.
3-4
A note was added to the "CS81" pin tables for AGLN060, AGLN060Z, AGLN125,
AGLN125Z, AGLN250, and AGLN250Z indicating that pins F1 and F2 must be grounded
(SAR 25007).
4-9,
through
4-14
A note was added to the "CS81" and "VQ100" pin tables for AGLN060 and AGLN060Z
stating that bus hold is not available for pin H7 or pin 45 (SAR 24079).
4-9,
4-24
The AGLN250 function for pin C8 in the "CS81" table was revised (SAR 22134).
4-13
Revision
Changes
Page
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