参数资料
型号: AGLP030V2-VQG128
厂商: Microsemi SoC
文件页数: 116/134页
文件大小: 0K
描述: IC FPGA IGLOO PLUS 30K 128-VQFN
标准包装: 90
系列: IGLOO PLUS
逻辑元件/单元数: 792
输入/输出数: 101
门数: 30000
电源电压: 1.14 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 128-TQFP
供应商设备封装: 128-VTQFP(14x14)
IGLOO PLUS DC and Switching Characteristics
2-68
Revision 16
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN, WEN setup time
0.68
ns
tENH
REN, WEN hold time
0.13
ns
tBKS
BLK setup time
1.37
ns
tBKH
BLK hold time
0.13
ns
tDS
Input data (DIN) setup time
0.59
ns
tDH
Input data (DIN) hold time
0.30
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
2.94
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
2.55
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
1.51
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address – applicable
to closing edge
0.29
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
0.24
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
0.40
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
1.72
ns
RESET Low to data out Low on DOUT (pipelined)
1.72
ns
tREMRSTB
RESET removal
0.51
ns
tRECRSTB
RESET recovery
2.68
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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