参数资料
型号: AGLP030V5-CS201
厂商: Microsemi SoC
文件页数: 92/134页
文件大小: 0K
描述: IC FPGA IGLOO PLUS 30K 201-CSP
标准包装: 384
系列: IGLOO PLUS
逻辑元件/单元数: 792
输入/输出数: 120
门数: 30000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 201-VFBGA,CSBGA
供应商设备封装: 201-CSP(8x8)
IGLOO PLUS DC and Switching Characteristics
2-46
Revision 16
1.2 V DC Core Voltage
Table 2-75 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tICLKQ
Clock-to-Q of the Input Data Register
0.66
ns
tISUD
Data Setup Time for the Input Data Register
0.43
ns
tIHD
Data Hold Time for the Input Data Register
0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.86
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.86
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.24
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.24
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.19
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.19
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.31
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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