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参数资料
型号： AGLP060V5-CS201
元件分类： FPGA
英文描述： FPGA, 1584 CLBS, 60000 GATES, PBGA201
封装： 8 X 8 MM, 0.89 MM HEIGHT, 0.5 MM PITCH, CSP-201
文件页数： 47/128页
文件大小： 4383K
代理商： AGLP060V5-CS201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 11
Table 2-16 Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device-Specific Static Power (mW)
AGLP125
AGLP060
AGLP030
PDC1
Array static power in Active mode
See Table 2-12 on page 2-8
PDC2
Array static power in Static (Idle) mode
See Table 2-11 on page 2-8
PDC3
Array static power in Flash*Freeze mode
See Table 2-9 on page 2-7
PDC4
Static PLL contribution
1.841
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-12 on page 2-8
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero Integrated Design Environment (IDE) software.
Table 2-17 Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Dynamic Power
(W/MHz)
AGLP125
AGLP060 AGLP030
PAC1
Clock contribution of a Global Rib
7.07
5.96
PAC2
Clock contribution of a Global Spine
0.52
0.26
PAC3
Clock contribution of a VersaTile row
0.52
PAC4
Clock contribution of a VersaTile used as a sequential module
0.07
PAC5
First contribution of a VersaTile used as a sequential module
0.045
PAC6
Second contribution of a VersaTile used as a sequential module
0.186
PAC7
Contribution of a VersaTile used as a combinatorial module
0.11
PAC8
Average contribution of a routing net
0.45
PAC9
Contribution of an I/O input pin (standard-dependent)
See Table 2-13 on page 2-9
PAC10
Contribution of an I/O output pin (standard-dependent)
See Table 2-14 on page 2-9
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic contribution for PLL
2.10
相关PDF资料
PDF描述
AGLP060V5-CS289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V5-CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V5-CSG201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V5-CSG201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V5-CSG289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
相关代理商/技术参数
参数描述
AGLP060V5-CS201I 功能描述:IC FPGA IGLOO PLUS 60K 201-CSP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO PLUS 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
AGLP060-V5CS289 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V5-CS289 功能描述:IC FPGA IGLOO PLUS 60K 289-CSP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO PLUS 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
AGLP060-V5CS289ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060-V5CS289I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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