参数资料
型号: AGLP060V5-CSG289I
厂商: Microsemi SoC
文件页数: 103/134页
文件大小: 0K
描述: IC FPGA IGLOO PLUS 60K 289-CSP
标准包装: 152
系列: IGLOO PLUS
逻辑元件/单元数: 1584
RAM 位总计: 18432
输入/输出数: 157
门数: 60000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 289-TFBGA,CSBGA
供应商设备封装: 289-CSP(14x14)
IGLOO PLUS DC and Switching Characteristics
2-56
Revision 16
1.2 V DC Core Voltage
Table 2-83 Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
1.61
ns
tSUD
Data Setup Time for the Core Register
1.17
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
1.29
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.87
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.89
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.24
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.46
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.46
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.95
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.95
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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