参数资料
型号: AGLP060V5CS289I
元件分类: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA289
封装: 14 X 14 MM , 1.2 MM HEIGHT, 0.8 MM PITCH, CSP-289
文件页数: 99/128页
文件大小: 4383K
代理商: AGLP060V5CS289I
IGLOO PLUS DC and Switching Characteristics
2- 58
R e v i sio n 1 1
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-84 AGLP030 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.21
1.42
ns
tRCKH
Input High Delay for Global Clock
1.23
1.49
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.27
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-85 AGLP060 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
1.32
1.62
ns
tRCKH
Input High Delay for Global Clock
1.34
1.72
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.38
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
相关PDF资料
PDF描述
AGLP060V5CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V5CSG201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V5CSG201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V5CSG289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V5CSG289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
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