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参数资料
型号： AGLP060V5CSG201I
元件分类： FPGA
英文描述： FPGA, 1584 CLBS, 60000 GATES, PBGA201
封装： 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件页数： 49/128页
文件大小： 4383K
代理商： AGLP060V5CSG201I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 13
FCLK is the global clock signal frequency.
NS-CELL is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
β
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on
page 2-14.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.
1
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相关代理商/技术参数
参数描述
AGLP060V5-CSG201I 功能描述:IC FPGA IGLOO PLUS 60K 201-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO PLUS 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
AGLP060-V5CSG289 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060V5-CSG289 功能描述:IC FPGA IGLOO PLUS 60K 289-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO PLUS 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
AGLP060-V5CSG289ES 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP060-V5CSG289I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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