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参数资料
| 型号： | AGLP125V5-CSG289I |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| 封装： | 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289 |
| 文件页数： | 13/128页 |
| 文件大小： | 4383K |
| 代理商： | AGLP125V5-CSG289I |
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IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
1-5
VersaTiles
The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS
core tiles. The IGLOO PLUS VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-3 for VersaTile configurations.
User Nonvolatile FlashROM
Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The
FlashROM can be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management
The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The
core can be individually programmed (erased and written), and on-chip AES decryption can be used
selectively to securely load data over public networks (except in AGLP030 devices), as in security keys
stored in the FlashROM for a user design.
The FlashROM can be programmed via the JTAG programming interface, and its contents can be read
back either through the JTAG programming interface or via direct FPGA core addressing. Note that the
FlashROM can only be programmed from the JTAG interface and cannot be programmed from the
internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte
basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks
and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the
FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM
address define the byte.
The Actel IGLOO PLUS development software solutions, Libero Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part. Another
feature allows the inclusion of static data for system version control. Data for the FlashROM can be
generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive
programming file support is also included to allow for easy programming of large numbers of parts with
differing FlashROM contents.
Figure 1-3
VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
相关PDF资料 |
PDF描述 |
|---|---|
| AGLP125V5-CSG289 | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP125V5CS281I | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| AGLP125V5CS281 | FPGA, 3120 CLBS, 125000 GATES, PBGA281 |
| AGLP125V5CS289I | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
| AGLP125V5CS289 | FPGA, 3120 CLBS, 125000 GATES, PBGA289 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AGLP125-V5CSG289PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-FCS281 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 125K GATES 1024 CELLS 130NM 1.5V 281CSP - Trays |
| AGLP125-V5FCS289 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V5-FCS289 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 125K GATES 1024 CELLS 130NM 1.5V 289CSP - Trays |
| AGLP125-V5FCS289ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
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