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参数资料
型号： AGLP125V5CSG289I
元件分类： FPGA
英文描述： FPGA, 3120 CLBS, 125000 GATES, PBGA289
封装： 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
文件页数： 48/128页
文件大小： 4383K
代理商： AGLP125V5CSG289I
IGLOO PLUS DC and Switching Characteristics
2- 12
R e v i sio n 1 1
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software.
The power calculation methodology described below uses the following variables:
The number of PLLs as well as the number and the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on
page 2-14.
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on
page 2-14.
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption.
PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5
NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in
Table 2-19 on page 2-14.
NROW is the number of VersaTile rows used in the design—guidelines are provided in
Table 2-19 on page 2-14.
Table 2-18 Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Static Power (mW)
AGLP125
AGLP060
AGLP030
PDC1
Array static power in Active mode
See Table 2-12 on page 2-8
PDC2
Array static power in Static (Idle) mode
See Table 2-11 on page 2-8
PDC3
Array static power in Flash*Freeze mode
See Table 2-9 on page 2-7
PDC4
Static PLL contribution
0.901
PDC5
Bank quiescent power (VCCI-dependent)
See Table 2-12 on page 2-8
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero IDE software.
相关PDF资料
PDF描述
AGLP125V5CSG289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP060V2-CS201I FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CS201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CS289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
AGLP060V2-CS289 FPGA, 1584 CLBS, 60000 GATES, PBGA289
相关代理商/技术参数
参数描述
AGLP125-V5CSG289I 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V5-CSG289I 功能描述:IC FPGA IGLOO PLUS 125K 289-CSP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO PLUS 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17）
AGLP125-V5CSG289PP 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
AGLP125V5-FCS281 制造商:Microsemi Corporation 功能描述:FPGA IGLOO PLUS 125K GATES 1024 CELLS 130NM 1.5V 281CSP - Trays
AGLP125-V5FCS289 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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