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参数资料
| 型号： | AK4112B |
| 厂商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | HIGH FEATURE 96kHz 24BIT DIR |
| 中文描述： | 特写96kHz的24位高迪尔 |
| 文件页数： | 7/30页 |
| 文件大小： | 334K |
| 代理商： | AK4112B |
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ASAHI KASEI
[AK4112B]
MS0078-E-02
2004/04
- 15 -
Error Handling
There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and
it is “L” when the PLL is OFF (Clock Operation Mode 1).
1. Unlock Error
: “H” when the PLL goes UNLOCK state.
2. Parity Error
: Updated every sub-frame cycle.
3. Biphase Error
: Updated every sub-frame cycle
4. Frame length Error
: Updated every sub-frame cycle
5. STC (Status Change) flag=“1”
: Holds “1” until reading 03H.
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it
maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins
when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.
When unlock state, the channel status bits are not updated and the previous data is maintained.
Error
AUTO
SDTO
V
Unlock Error
“L”
Parity Error
Output
Previous Data
Output
Biphase Error
Output
Previous Data
Output
Frame Length Error
Output
Previous Data
Output
Table 11. Error handling (Parallel Mode)
In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and
Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked
by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the
last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made
every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after
reset.
Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors
(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,
it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the
previous data is maintained.
Register
Pin
Error
& Status
UNLOCK
PAR
BIP
FRERR
STC
AUTO
SDTO
V
TX
Unlock Error
1
0
“L”
Output
Parity Error
0
1
0
Output
Previous Data
Output
Biphase Error
0
1
0
Output
Previous Data
Output
Frame Length Error
0
1
0
Output
Previous Data
Output
Status change
0
1
Output
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
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