- 您现在的位置：买卖IC网 > PDF目录378309 > AL4V185 (AverLogic Technologies, Inc.) 16K, 64K-Bit Line FIFO PDF资料下载
参数资料
| 型号： | AL4V185 |
| 厂商： | AverLogic Technologies, Inc. |
| 英文描述： | 16K, 64K-Bit Line FIFO |
| 中文描述： | 16K的，64K的位线先进先出 |
| 文件页数： | 2/2页 |
| 文件大小： | 39K |
| 代理商： | AL4V185 |
A
VER
L
OGIC
T
ECHNOLOGIES
,
I
NC
.
TEL
:
1
408
361-0400
A
VER
L
OGIC
T
ECHNOLOGIES
,
C
ORP
.
TEL
:
886
2-87523988
e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw
e-mail:
sales_usa@averlogic.com
URL: www.averlogic.com
October 30, 2004
(1k , 4k) x18
Memory
Array
Input
Buffer
Output
Buffer
Write
Control
Logic
Write Pointer
Read
Control
Logic
Read Pointer
Timing &
Control Logic
Offset
Regissers
Input data bus
Output data bus
/OE
WCLK
/WEN
RCLK
/REN
/BEB
/IW
/OW
Figure 1. AL4V18x FIFO Block Diagram
/RRSTB
/WRSTB
The 18bit input and output ports operate
independently at a maximum speed of 100 MHz.
The built-in address decoder and pointer
managing circuits provide a straightforward bus
interface to serially read/write memory that
reduces inter-chip design efforts. The AL4V18x
embedded memory array and high performance
process technologies with extended controller
functions (read skip, fixed and programmable
status flags... etc.) offer flexible memory
management.
These FIFOs support up to 18-bit input and output
data bus-width that is controlled by separate clock
and enable signals respectively. The input data is
acquired at each rising edge of a free running
write clock while a write enable control pin is
asserted. The output data is available after each
rising edge of a free running read clock while a
read enable and output enable control pins are
asserted. When output enable (/OE) is LOW, the
data output bus is active. If /OE is HIGH, the
output data bus will be in a high-impedance. This
signal can control whether the data is going to be
skipped during the read operation.
Bus-Matching feature can flexibly configure input
and output bus width. The chip can automatically
convert the input data bus width to match up
output data bus width by packing or unpacking
the data. A Big-Endian/Little-Endian data word
format is provided to invert the read-in bytes
sequence for output. And the Retransmit function
allows data to be reread from the FIFO more than
once.
These chips are available as a 64pin STQFP
Package.
D
ISTRIBUTED BY
:
相关PDF资料 |
PDF描述 |
|---|---|
| AL4V95 | 16K, 64K-Bit Line FIFO |
| AL4V93 | 16K, 64K-Bit Line FIFO |
| AL5DA002 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA003 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
| AL5DA004 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AL4V93 | 制造商:AVERLOGIC 制造商全称:AVERLOGIC 功能描述:16K, 64K-Bit Line FIFO |
| AL4V95 | 制造商:AVERLOGIC 制造商全称:AVERLOGIC 功能描述:16K, 64K-Bit Line FIFO |
| AL5 | 制造商:Panasonic Industrial Company 功能描述:CLAMP |
| AL-5 | 制造商:Richco 功能描述:P CLIP ALUMINIUM 7.9MM PK100 制造商:Richco 功能描述:P CLIP, ALUMINIUM, 7.9MM, PK100 制造商:Richco 功能描述:P CLIP, ALUMINIUM, 7.9MM, PK100; Clip Style:P Clip; Clip Diameter:7.9mm; Mounting Hole Dia:5.2mm; SVHC:No SVHC (18-Jun-2012); External Length / Height:14.2mm; External Width:9.5mm; Fastener Material:Aluminium; Fixing Hole ;RoHS Compliant: Yes |
| AL-500 | 制造商:INSTRUMENT TRANSFORMER 功能描述:CURRENT TRANSFORMER ;ROHS COMPLIANT: NA |
发布紧急采购，3分钟左右您将得到回复。