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参数资料
| 型号： | AL4V93 |
| 厂商： | AverLogic Technologies, Inc. |
| 英文描述： | 16K, 64K-Bit Line FIFO |
| 中文描述： | 16K的，64K的位线先进先出 |
| 文件页数： | 2/2页 |
| 文件大小： | 34K |
| 代理商： | AL4V93 |
A
VER
L
OGIC
T
ECHNOLOGIES
,
I
NC
.
TEL
:
1
408
361-0400
A
VER
L
OGIC
T
ECHNOLOGIES
,
C
ORP
.
TEL
:
886
2-87523988
e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw
e-mail:
sales_usa@averlogic.com
URL: www.averlogic.com
October 30, 2004
(2k, 8k) x9
Memory
Array
Input
Buffer
Output
Buffer
Write
Control
Logic
Write Pointer
Read
Control
Logic
Read Pointer
Timing & Logic
Control
Offset
Regissers
Input data bus
Output data bus
/OE
WCLK
/WEN
/WRST
RCLK
/REN
/RRST
AL4V9x FIFO Block Diagram
The 9-bit input and output ports operate
independently at a maximum speed of
100MHz. The built-in address decoder and
pointer
managing
straightforward bus interface to serially
read/write memory that reduces inter-chip
design efforts. The AL4V9x embedded
memory array and high performance process
technologies
with
functions (read skip, fixed and programmable
status flags... etc.) offer flexible memory
management.
The input data is synchronous with a free-
running clock (WCLK), and input-enable pins
(/WEN). Data is written into the FIFO on
every clock when enable pins are asserted.
The output is synchronous with the other free-
running clock (RCLK) and enables (/REN).
An Output Enable pin (/OE) is provided at the
read port for tri-state control of the output port.
The AL4V9x series are operating in 3.3V
power supply with 5V signal tolerant input.
These chips are available as a 32-pin TQFP
Package.
circuits
provide
a
extended
controller
D
ISTRIBUTED BY
:
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| AL5DA004 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
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| AL5DA006 | 3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit |
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参数描述 |
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| AL4V95 | 制造商:AVERLOGIC 制造商全称:AVERLOGIC 功能描述:16K, 64K-Bit Line FIFO |
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