参数资料
型号: ALQ15FG48
元件分类: 电源模块
英文描述: 2-OUTPUT 60 W DC-DC REG PWR SUPPLY MODULE
文件页数: 14/18页
文件大小: 863K
代理商: ALQ15FG48
Technical Reference Notes
ALQ15XX48X Series
(Open Frame Dual Output Quarter Brick)
MODEL: ALQ15 SERIES
SHEET 5 OF 18
OCTOBER 4, 2002 - REVISION A1
Electrical Specifications (continued)
OUTPUT SPECIFICATIONS
Parameter
Device
Symbol
Min
Typ
Max
Unit
Regulation
Load
4
Conditions: IO = 1A to IO,max;
VIN =VIN,nom
All
-
1.0
%Vo
Temperature
Conditions: TA = -40 C to +65 C;
VIN = VIN,nom; IO = IO,max
All
-
2
%Vo
Output Ripple and Noise:
Peak-to-Peak
5
Conditions: IO = IO,max; VIN =VIN,nom;
BW = 20 MHz;
TA =25
oC
3.3
2.5
1.8
1.5
5.0
-
30
mVPK-PK
mVPK-PK
External Load Capacitance
6
All
-
10000
F
Over Current Limit Inception
Conditions: Vo = 90% VO,nom;
IO2 = IO,min; VIN = VIN,nom
Characteristics: Hiccup mode,
auto-recovery
All
5.0V
IO,OCP
IO,OCP
16.5
13.2
-
25
20
A
Output Short Circuit
Conditions: VIN = VIN,nom; IO2 = 0A
TA = 25 C
All
IOPK
IORMS
IODC
IINS
-
28
5
1
150
APK
ARMS
A
mA
Efficiency
Conditions: VIN = VIN,nom; TA = 25 C
PO = PO,max, balanced
current loading
FG
FY
GM
AF
η
85.0
84.0
81.0
87.5
87.0
86.0
83.0
88.5
%
Switching Frequency
Note: Can be determined from output
ripple waveform
All
-
225
250
275
KHz
NOTE: 4. Channel under test shall follow the specified conditions while the other channel is set to min load, 0A.
5. Channel under test shall be set to full load with the other channel set to IO, min - See Fig 2.
6. Refer to YSC plots on Fig 18 and 19 to determine loop stability at various output load impedance.
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