参数资料
型号: AM29F010B70JE
厂商: Spansion Inc.
英文描述: LCD Character display; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes
中文描述: 1兆位(128亩× 8位)的CMOS 5.0伏只,统一部门快闪记忆体
文件页数: 12/35页
文件大小: 849K
代理商: AM29F010B70JE
November 18, 2002
Am29F010B
11
Table 3.
Am29F010B Autoselect Codes (High Voltage Method)
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 22337. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by
spurious system level signals during V
CC
power-up
and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Description
CE#
OE#
WE#
A16
to
A14
A13
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
Manufacturer ID
:
AMD
L
L
H
X
X
V
ID
X
L
X
L
L
01h
Device ID: Am29F010B
L
L
H
X
X
V
ID
X
L
X
L
H
20h
Sector Protection Verification
L
L
H
SA
X
V
ID
X
L
X
H
L
01h
(protected)
00h
(unprotected)
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